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SI5XX5X7-EVB 데이터시트(PDF) 2 Page - Silicon Laboratories |
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SI5XX5X7-EVB 데이터시트(HTML) 2 Page - Silicon Laboratories |
2 / 8 page Si5xx5x7-EVB 2 Rev. 0.3 1. Functional Description The Si5xx5x7-EVB provides access to all signals for configuring and operating the device. This board allows evaluation of the Si55x/595 VCXO device either by itself (open-loop) or within a prototype PLL (closed-loop). The performance of the Si53x/590/591 XO device can also be evaluated on this board (the Vc port is not used for XO devices). 1.1. Power Supply The Si55x/Si53x/59x devices support operation from nominal voltages of 1.8, 2.5, and 3.3 V. Review the device data sheet and part number for allowed configurations of output buffer type and device power supply. 1.2. Voltage Control for VCXOs The voltage control (VC) input of the Si55x/595 device is conveniently accessible through an SMA jack (J3) but can also be driven (and observed) through 100 mil- centered posts (JP4). For prototyping purposes, two 0603 solder pads are located near the device VC input (R3 and C3). A traditional PLL might use these as a single-time-constant low-pass filter (RC filter). The EVB is shipped with a 0 resistor soldered at R3; C3 is left open. The voltage control input is not used for XO devices. 1.3. Output Clock Because the Si55x/Si53x/59x devices can support an LVPECL buffer type (in addition to LVDS and CMOS), pulldown resistors (R1 and R2) are available for proper output biasing. For LVPECL buffers, biasing can be achieved through a variety of equivalent circuits; the Si5xx5x7-EVB allows for 130 pulldown resistors. After the output biasing, the high-speed outputs are dc- blocked for connection to differently biased inputs, such as standard test equipment or a phase detector EVB. Please review “1.4. Preparing the EVB” for non-LVPECL devices. 1.4. Preparing the EVB By default, the evaluation board is set up to accept LVPECL configured devices. This configuration uses 130 pull-down resistors to bias the LVPECL output stage. If an LVDS, CMOS, or CML based device is to be installed, the output biasing resistors, R1 and R2, should be removed. Table 1. Jumper Control Part Type JP1 JP2 JP3 JP4 Si530 N/A N/A OE N/A Si531 N/A N/A N/A OE Si532 N/A N/A OE Freq Sel Si533 N/A N/A Freq Sel OE Si534 Freq Sel1 Freq Sel2 OE N/A Si550 N/A N/A OE VC Si552 N/A N/A Freq Sel VC Si554 Freq Sel1 Freq Sel2 OE VC Si590 N/A N/A OE N/A Si591 N/A N/A N/A OE Si595 N/A N/A OE VC Notes: 1. With jumper(s) installed, signal(s) are driven low. 2. With jumper(s) not installed, signal(s) are pulled high. |
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