전자부품 데이터시트 검색엔진 |
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AD9248BST-65 데이터시트(PDF) 6 Page - Analog Devices |
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AD9248BST-65 데이터시트(HTML) 6 Page - Analog Devices |
6 / 23 page AD9248 Preliminary Technical Data Rev. PrE | Page 6 of 23 SWITCHING SPECIFICATIONS Table 3. Switching Specifications Test AD9248BST/BCP- 20 AD9248BST/BCP- 40 AD9248BST/BCP- 65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE Max Conversion Rate Full VI 20 40 65 MSPS Min Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulsewidth High 1 Full V 15.0 8.8 6.2 ns CLK Pulsewidth Low 1 Full V 15.0 8.8 6.2 ns DATA OUTPUT PARAMETER Output Delay 2 (t PD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 Ps rms Wake-Up Time 3 Full V 2.5 2.5 2.5 ms OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 1 The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC 20). 2 Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Specifications subject to change without notice. |
유사한 부품 번호 - AD9248BST-65 |
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유사한 설명 - AD9248BST-65 |
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