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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TP3420AV 데이터시트(PDF) 4 Page - National Semiconductor (TI) |
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TP3420AV 데이터시트(HTML) 4 Page - National Semiconductor (TI) |
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4 / 32 page  Pin Descriptions (Continued) TABLE 1. Alternate Pin Function Assignment Device Mode P2 - Pin 8 P1 - Pin 18 Function x 2 Function x 1,x0 TEM DENx (Note 3) 0 (Note 3) LSD 00 (Note 3) SCLK 1 DENr 01 SCLK 10 DENx 11 TES DENx 0 LSD 00 (Note 3) SCLK (Note 3) 1 (Note 3) DENr 01 SCLK 10 DENx 11 NTA DENx (Note 3) 0 (Note 3) LSD 00 (Note 3) NTF SCLK 1 DENr 01 SCLK 10 DENx 11 MMA DENx (Note 3) 0 (Note 3) LSD 00 (Note 3) SCLK 1 DENr 01 SCLK 10 DENx 11 PINDEF command is coded as X’EX (i.e. 11100x2x1x0). Note 3: Default pin function after device mode selection. SIGNAL DESCRIPTION SCLK is an output synchronized clock at the frequency se- lected by the Digital Interface Format. This clock is phase-locked to the received line signal, and is intended to be used as the BCLK source. LSD is the Line Signal Output, an n-channel open-drain out- put that is normally high-impedance, but pulls low when the device is powered down and a received line signal is de- tected. It is intended to be used to “wake-up” a microproces- sor from a low-power idle mode. This output is a high imped- ance when the device is powered up. DENr is a CMOS output that is normally low and pulses high to indicate the active bit times for “D” channel Receive data at the B r output pin. It is intended to be gated with BCLK to control the shifting of data from the TP3420A receive buffer to a layer 2 device. DENx is a CMOS output that is normally low and pulses high to indicate the active bit times for D channel Transmit data at the B x input. It is intended to be gated with BCLK to control the shifting of data from a layer 2 device to the TP3420A’s transmit buffer. In NT mode, this pulse occurs every 8 kHz frame and indicates the location of D channel data input on the B x pin. ADDITIONAL PIN CONFIGURATION The TP3420A in TEM mode can be configured to interface with the Motorola layer-2 devices such as the MC68302 and the MC145488. A PINDEF (X’E1) command followed by a DCKE (X’F1) command will alter the TP3420A pin functions as shown in Table 2. Other configurations of PINDEF are not supported. TABLE 2. Pin Number Pin Function 8 DTCK 11 TxD 18 DRCK Where: • DCLK is a burst clock output intended to be used as a clock source for the transmitter of an HDLC device. • TxD is an input being sampled on the rising edge of DCLK during the active D-channel timeslot. • DRCK is a burst clock output which pulses 2 BCLK peri- ods every 8 kHz frame. This output is intended to be used as a clock source for the receiver of an HDLC device. The D-channel data at B r is transmitted on the falling edge of the DRCK. Functional Description DEVICE MODES The TP3420A can be programmed into one of four possible modes. For NT applications select NT Adaptive timing (NTA) for all wiring configurations except a Short Passive Bus, for which NT Fixed Timing (NTF) should be selected. In TE ap- plications, select TE Master mode (TEM) for the device to be the master (source) of clocks at the digital interface, or select TE Slave mode (TES) for the digital interface to accept clocks from the system. Selection of these modes is described in the section on Con- trol Register instructions. POWER-ON DEVICE CONDITIONS Following the initial application of power, the TP3420A SID enters the power-down (de-activated) state, in which all the internal circuits including the Master oscillator are inactive and in a low power state except for the Line-Signal Detect circuit; the line outputs L o+/Lo− are in a high impedance state and the Digital System Interface is inactive. All bits in the Control Register power-up as indicated in Table 1.In both NT and TE modes, a Line-Signal Detect circuit monitors the line while the device is powered-down, to enable loop transmission to be initiated from either end. POWER-OFF DEVICE CONDITION When power to the TP3420A is turned off, the Line outputs L o+/Lo− go into high impedance state, hence if a TE on a passive bus lost power its transmit impedance still meets the specification without any external relay (see AN665 for exter- nal protection components). The receiver impedance also remains in specification. LINE CODING AND FRAME FORMAT For both directions of transmission, Alternate-Mark Inversion (AMI) coding with inverted binary is used, as illustrated in Figure 1. This coding rule requires that a binary ONE is rep- resented by 0V high impedance output, whereas a binary ZERO is represented by a positive or negative-going 100% duty-cycle pulse. Normally, binary ZEROs alternate in polar- ity to maintain a d.c.-balanced line signal. The frame format used in the TP3420A SID follows the CCITT recommendation specified in I.430 and illustrated in Figure 2. Each complete frame consists of 48 bits, with a line bit rate of 192 kb/s, giving a frame repetition rate of 4 kHz. A violation of the AMI coding rule is used to indicate a frame www.national.com 4 |
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