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TPD2S300 데이터시트(PDF) 7 Page - Texas Instruments |
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TPD2S300 데이터시트(HTML) 7 Page - Texas Instruments |
7 / 37 page 7 TPD2S300 www.ti.com SLVSDL1 – APRIL 2017 Product Folder Links: TPD2S300 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 6.7 Timing Requirements MIN NOM MAX UNIT POWER-ON AND POWER-OFF TIMINGS tON Time from crossing rising VPWR UVLO until CC OVP FETs are on. VPWR slew rate = 0.347 V/µs 200 µs dVPWR_OFF/ dt Minimum slew rate allowed to guarantee CC FETs turn off during a power off –0.5 V/µs OVERVOLTAGE PROTECTION tOVP_RESPON SE_CC OVP response time on the CC pins. Time from OVP asserted until OVP FETs turn off. Hot-Plug C_CCx to 24 V with a 1-m cable. C_CCx slew rate = 4 V/ns. Place a 30-Ω on CCx 145 ns tOVP_RECOVE RY_CC OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 10.8 V. Step C_CCx down from 6.3 V to 3.3 V at a 0.343-V/µs slew rate 30 µs tOVP_RECOVE RY_CC OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 3.3 V. Step C_CCx down from 6.3 V to 0.49 V at a 0.321-V/µs slew rate 200 µs tOVP_FLT_ASS ERTION Time from OVP asserted to FLT assertion.FLT assertion is when the FLT pin reaches 10% of its starting value. C_CCx from 0 V to 6.3 V at a 0.645- V/µs slew rate 1 µs tOVP_FLT_DE ASSERTION Time from OVP removal to FLT deassertion. FLT deassertion is when the FLT pin reaches 90% of its final value. C_CCx from 6.3 V to 0 V at a 0.696-V/µs slew rate 20 µs |
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