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TMP464AIRGTT 데이터시트(PDF) 6 Page - Texas Instruments |
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TMP464AIRGTT 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 43 page P S t(HD:STA) t(HD:DAT) t(HIGH) t(SU:DAT) t(SU:STO) S P SCL SDA t(LOW) tr tf VIH VIL t(BUF) VIH VIL t(SU:STA) 6 TMP464 SBOS835 – MAY 2017 www.ti.com Product Folder Links: TMP464 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) The maximum tHD;DAT can be 0.9 µs for fast mode, and is less than the maximum tVD;DAT by a transition time. (2) tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse). 6.6 Two-Wire Timing Requirements at TA = –40°C to +125°C and V+ = 1.7 V to 3.6 V (unless otherwise noted) The master and the slave have the same V+ value. Values are based on statistical analysis of samples tested during initial release. MIN MAX UNIT fSCL SCL operating frequency Fast mode 0.001 0.4 MHz High-speed mode 0.001 2.56 tBUF Bus free time between stop and start condition Fast mode 1300 ns High-speed mode 160 tHD;STA Hold time after repeated start condition. After this period, the first clock is generated. Fast mode 600 ns High-speed mode 160 tSU;STA Repeated start condition setup time Fast mode 600 ns High-speed mode 160 tSU;STO Stop condition setup time Fast mode 600 ns High-speed mode 160 tHD;DAT Data hold time Fast mode 0 (1)ns High-speed mode 0 130 tVD;DAT Data valid time(2) Fast mode 0 900 ns High-speed mode — — tSU;DAT Data setup time Fast mode 100 ns High-speed mode 20 tLOW SCL clock low period Fast mode 1300 ns High-speed mode 250 tHIGH SCL clock high period Fast mode 600 ns High-speed mode 60 tF – SDA Data fall time Fast mode 20 × (V+ / 5.5) 300 ns High-speed mode 100 tF, tR – SCL Clock fall and rise time Fast mode 300 ns High-speed mode 40 tR Rise time for SCL ≤ 100 kHz Fast mode 1000 ns High-speed mode Serial bus timeout Fast mode 15 20 ms High-speed mode 15 20 Figure 1. Two-Wire Timing Diagram |
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