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LC3564BT 데이터시트(PDF) 9 Page - Sanyo Semicon Device

부품명 LC3564BT
상세설명  64K (8192-word8-bit) SRAM with OE, CE1, and CE2 Control Pins
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제조업체  SANYO [Sanyo Semicon Device]
홈페이지  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC3564BT 데이터시트(HTML) 9 Page - Sanyo Semicon Device

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PS No. 5804-9/9
LC3564B, BS, BM, BT-70/10
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Data retention supply voltage
VDR
VCE2 ≤ 0.2 V or
2.0
5.5
µA
VCE1 ≥ VCC – 0.2 V, VCE2 ≥ VCC – 0.2 V
VCC = 3V, VCE2 ≤ 0.2 V,
Ta
≤ 70°C
0.8
µA
Data retention supply current
ICCDR
or VCE1 ≥ VCC – 0.2 V,
VCE2 ≥ VCC – 0.2 V
Ta
≤ 85°C
2.5
Chip enable setup time
tCDR
0
ns
Chip enable hold time
tR
tRC*
ns
Data Retention Characteristics at Ta = –40 to +85°C
Note *: tRC is the read cycle time.
Note *:In 5-V operation: 4.5 V
In 3-V operation: 2.7 V
Data retention mode
Data Retention Waveforms (1): CE1 Control
Notes on Circuit Design
When actually design a circuit using these devices, take the following points into consideration and design the circuit so
that none of the maximum rating items are ever exceeded.
• Variations in the supply voltage
• Variations in the electrical characteristics of components such as semiconductor devices, resistors, and capacitors.
• Ambient temperature
• Variations in input and clock signals
• Possible application of abnormal pulses
Also, these devices must be operated within the ranges stipulated in the allowable operating ranges.
If CMOS IC input pins are left open, intermediate potential input voltages may occur leading to incorrect operation due
to through currents or other phenomenon. Applications must handle unused input pins appropriately.
Data Retention Waveforms (2): CE2 Control
Data retention mode


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