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DA7838.002 20 September, 2000 2 (9) 3,1&21),*85$7,21 Top marking: YYWW = Year Week, XXXXX.X = Lot Number, =ESD Indicator 3,1'(6&5,37,21 3LQ QDPH 3LQ QR ,2 )XQFWLRQ TSL 1 I Timing select. 0 selects asynchronous sampling timing 16 x TXC from pin 2, TMG. 1 selects asynchronous sampling timing 256...8192 x TXC from pin 2, TMG. TMG 2 I Timing. Square wave timing signal 16 x TXC (TSL=0) or 256...8192 x TXC (TSL=1). Max f=10 MHz. OSC 3 O Oscillator. Output for crystal. If used, the crystal is connected between pins 2 and 3. TXC 4 I Transmitter timing. Synchronous square wave timing for transmitter. The transmitted data output, TDO is synchronized to the rising edge of TXC. The duty cycle of TXC has to be 50% +/- 5%. CL1 5 I CL2 6 I Character length. The total character length including one start bit, one stop bit and possible parity bit is selected with the CL1 and CL2 signals. XESR 7 I Extended signalling rate. The tolerance of the synchronous bit rate can be: XESR = 1 (basic signalling rate) TXC -2.5%...+1.0% XESR = 0 (extended signalling rate) TXC -2.5%...2.3% VSS 8 G Ground TDI 9 I Transmitter data input. 1 = mark or stop bit, 0 = space, start or break signal TDO 10 O Transmitter data output. The output data is synchronized to the synchronous timing signal TXC (pin 4). 1 = mark, 0 = space XASY 11 I Asynchronous mode. XASY=0 Asynchronous transmission. XASY=1 Synchronous transmission. In synchronous transmission the converter is totally bypassed in both directions: TDI=TDO, RDI=RDO XHST 12 I Higher speed signalling timing. XHST = 1 normal synchronous to asynchronous conversion (Bell 212; CCITT V.22). XHST = 0 asynchronous to synchronous conversion with higher speed synchronous timing (TXC, RXC). TXC and RXC timing must be 1-2% higher than the normal bit rate in order to allow some overspeed in the asynchronous data. On the receiver side the RX buffer is deleted and the synchronous data RDI is directly connected to the asynchronous output RDO. RDO 13 O Receiver data output. RDO is the received data converted back to asynchronous mode. 1 = mark or stop bit, 0 = space, start or break signal RDI 14 I Receiver data input. 1 = mark, 0 = space. The received data must be synchronized to the receiver timing RXC from the synchronous channel (pin 15). RXC 15 I Receiver timing. Receiver square wave timing from the synchronous channel. The received data RDI must be synchronized to the rising edge of RXC. VDD 16 P Power supply PDIP 16 TSL TMG OSC TXC CL1 CL2 XESR VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD RXC RDI RDO XHST XASY TDO TDI TSL TMG OSC TXC CL1 CL2 XESR VSS 1 2 3 4 5 6 7 8 SO16 9 10 11 12 13 14 15 16 VDD RXC RDI RDO XHST XASY TDO TDI MAS7838N MAS7838S ÃÃÃÃ ÃÃÃ& '" ' Y Y Y Y Y Y ÃÃÃ` ` X X ÃÃÃÃ ÃÃÃ& '" ' Y Y Y Y Y Y ÃÃÃ` ` X X |
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