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AD9265BCPZ-105 데이터시트(PDF) 3 Page - Analog Devices |
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AD9265BCPZ-105 데이터시트(HTML) 3 Page - Analog Devices |
3 / 45 page AD9265 Data Sheet Rev. C | Page 2 of 44 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 ADC DC Specifications............................................................... 4 ADC AC Specifications ................................................................. 5 Digital Specifications ................................................................... 6 Switching Specifications ................................................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 Equivalent Circuits ......................................................................... 23 Theory of Operation ...................................................................... 25 ADC Architecture ...................................................................... 25 Analog Input Considerations.................................................... 25 Voltage Reference ....................................................................... 28 Clock Input Considerations...................................................... 29 Power Dissipation and Standby Mode .................................... 31 Digital Outputs ........................................................................... 32 Timing.......................................................................................... 32 Built-In Self-Test (BIST) and Output Test .................................. 33 Built-In Self-Test (BIST)............................................................ 33 Output Test Modes..................................................................... 33 Serial Port Interface (SPI).............................................................. 34 Configuration Using the SPI..................................................... 34 Hardware Interface..................................................................... 34 Configuration Without the SPI ................................................ 35 SPI Accessible Features.............................................................. 35 Memory Map .................................................................................. 36 Reading the Memory Map Register Table............................... 36 Memory Map Register Table..................................................... 37 Memory Map Register Descriptions........................................ 39 Applications Information .............................................................. 40 Design Guidelines ...................................................................... 40 Outline Dimensions....................................................................... 41 Ordering Guide .......................................................................... 41 REVISION HISTORY 8/13—Rev. B to Rev. C Changes to Data Clock Output (DCO) Section ......................... 32 Changes to Ordering Guide .......................................................... 41 3/13—Rev. A to Rev. B Changes to Table 17........................................................................ 37 Updated Outline Dimensions....................................................... 41 1/10—Rev. 0 to Rev. A Changes to Worst Other (Harmonic or Spur) Parameter, Table 2 ................................................................................................ 5 Changes to Figure 77...................................................................... 29 Changes to Input Clock Divider Section..................................... 30 Changes to Table 17........................................................................ 37 Updated Outline Dimensions....................................................... 41 10/09—Revision 0: Initial Version |
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