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AM79C875 데이터시트(PDF) 11 Page - Advanced Micro Devices |
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AM79C875 데이터시트(HTML) 11 Page - Advanced Micro Devices |
11 / 48 page Am79C875 11 MDIO Management Data I/O Input/Output, Pull-Down This pin is a bidirectional data interface used by the MAC to access management register within the Net- PHY™ 4LP device. This pin has an internal pull-down, therefore, it requires an external pull-up resistor (1.5 K Ω) as specified in IEEE-802.3 section 22. MDC Management Data Clock Input, Pull-Down This pin is the serial management clock which is used to clock MDIO data to the MAC. RST Reset Input, Pull-Up An active low input will force the NetPHY™ 4LP device to a known reset state. Reset also can be done through the internal power-on-reset or MII Register 0, bit 15. INTR Interrupt Tri-State This pin is true whenever the NetPHY™ 4LP device detects an event flagged as an interrupt. Events to be flagged are programmed in Register 17. Interrupts are cleared on Read. The polarity of INTR (active HIGH or active LOW) is set by Register 16, bit 14. The default is active LOW, which requires a 10 K Ω pull-up resistor. LED Port Note: Consult the LED Port Configuration section for appropriate pull-up and pull-down resistors. LEDDPX[0]/FX_DIS Port [0] Duplex LED Input/Output, Pull-Up Low LED indicates full-duplex and high indicates half- duplex. FX Mode: Pulled low at reset will put Port 3 in 100BASE-FX mode. LEDACT_LINK[0] Port [0] Transmit/Receive Activity LED Output, Pull-Up LED is output low for approximately 30 ms each time there is activity. LINK is an active low signal. This signal should have a 1k–4.7K Ω pull-up resistor. LEDSPD[0]/TP1_1 Port [0] Speed LED Input/Output, Pull-Up LED is output low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. TP1_1: Pulled low at reset will select transmit trans- former ratio to be 1.25:1. Default is 1:1 transformer. LEDDPX[1]/PHYAD[4] Port [1] Duplex LED Input/Output, Pull-Up LED low indicates full-duplex and high indicates half- duplex. PHY Address[4]. This is the first address bit received in the management frame, and one of three MSBs for MII management PHY address. The two LSBs, PHYAD [1:0] are internally wired to four ports: PHYAD [11]=Port3,..., PHYAD [00] = Port0. The PHYAD will also determine the scramble seed, this will help to reduce EMI when there are multiple ports switching at the same time. To set this pin, use pull-up or pull-down resistors in the range of 1 K Ω to 4.7 KΩ. LEDACT_LINK[1]/PHYAD[3] Port [1] Transmit/Receive Activity LED Input/Output, Pull-Up LED is output low for approximately 30 ms each time there is activity. LINK is an active low signal. PHY Address[3]. This is the second MSB and one of three MSB’s for MII management PHY address. To set this pin, use pull-up or pull-down resistors in the range of 1 K Ω to 4.7 KΩ. LEDSPD[1]/PHYAD[2] Port [1] Speed LED Input/Output, Pull-Up LED is output low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. PHY Address[2]. This is the third MSB and one of three MSB’s for MII management PHY address. To set this pin, use pull-up or pull-down resistors in the range of 1 K Ω to 4.7 KΩ. LEDDPX[2]/DPLX Port [2] Duplex LED Input/Output, Pull-Up LED low indicates full-duplex and high indicates half- duplex. DPLX: Full Duplex Mode Enable. This pin is logically OR’ed with a full-duplex enable MII control bit to gener- ate an internal full-duplex enable signal. When as- serted high, the NetPHY™ 4LP device operates in full- duplex mode as determined through Auto-Negotiation or software setting. When asserted low, the internal control bit (Register 0, bit 8) will determine the full-du- plex operating mode. LEDACT_LINK[2] Port [2] Transmit/Receive Activity LED Output, Pull-Up LED is output low for approximately 30 ms each time there is activity. LINK is an active low signal. This signal should have a 1k–4.7K Ω pull-up. LEDSPD[2]/FORCE100 Port [2] Speed LED Input/Output, Pull-Up LED is output low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. FORCE100: Force 100BASE-X Operation. When this signal is pulled high and ANEGA is low at reset, all ports will be forced to 100BASE-TX operation. When asserted low and ANEGA is low, all ports are forced to |
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