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ACE25QA160G 데이터시트(PDF) 7 Page - ACE Technology Co., LTD. |
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ACE25QA160G 데이터시트(HTML) 7 Page - ACE Technology Co., LTD. |
7 / 29 page ACE25QA160G 16M BIT SPI NOR FLASH VER 1.1 7 SRP bits The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, and BP0) become read-only bits and the Write Status Register (WRSR) instruction is not execution. The default value of SRP is 0. Write Protect Features (A) Software Protection: The Block Protect (BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change. (B) Hardware Protection: /WP going low to protected the BP0~BP2 bits and SRP bits. (C) Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from deep Power-Down Mode instruction. (D) Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector Erase, and Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. Status Register Memory Protection Protect Table Table 4. ACE25QA160G Status Register Memory Protection Status Register Content Memory Content BP2 BP1 BP0 Blocks Addresses Density Portion 0 0 0 NONE NONE NONE NONE 0 0 1 Sector 0 to 509 000000H-1FDFFFH 2040KB Lower 510/512 0 1 0 Sector 0 to 507 000000H-1FBFFFH 2032KB Lower 508/512 0 1 1 Sector 0 to 503 000000H-1F7FFFH 2016KB Lower 504/512 1 0 0 Sector 0 to 495 000000H-1EFFFFH 1984KB Lower 496/512 1 0 1 Sector 0 to 479 000000H-1DFFFFH 1920KB Lower 480/512 1 1 0 Sector 0 to 447 000000H-1BFFFFH 1792KB Lower 448/512 1 1 1 ALL 000000H-1FFFFFH 2048KB ALL |
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