PLQP0064KB-A datasheet(89/108 Pages) RENESAS

부품명	PLQP0064KB-A

상세설명	32 MHz 32-bit RX MCUs, 50 DMIPS

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R01DS0202EJ0120 Rev.1.20

Page 89 of 108

Jul 29, 2016

RX110 Group

5. Electrical Characteristics

5.6

Power-On Reset Circuit and Voltage Detection Circuit Characteristics

Note:

These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage

detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used

for voltage detection.

Note 1. n in the symbol Vdet1_n denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.

Note:

These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage

detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used

for voltage detection.

Note 1. n in the symbol Vdet2_n denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.

Note 2. Vdet2_3 selection can be used only when the CMPA2 pin input voltage is selected and cannot be used when the power supply

voltage (VCC) is selected.

Note 3. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.

Note 4. When OFS1.(STUPLVD1REN, FASTSTUP)

≠ 11b.

Note 5. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,

Vdet1, and Vdet2 for the POR/LVD.

Table 5.41

Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)

Conditions: 1.8 V

≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T

a = –40 to +105°C

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Voltage detection level

Power-on reset (POR)

VPOR

1.35

1.50

1.65

V

Figure 5.49,

Figure 5.50

Voltage detection circuit

(LVD1)*1

Vdet1_4

3.00

3.10

3.20

V

Figure 5.51

At falling edge VCC

Vdet1_5

2.91

3.00

3.09

Vdet1_6

2.81

2.90

2.99

Vdet1_7

2.70

2.79

2.88

Vdet1_8

2.60

2.68

2.76

Vdet1_9

2.50

2.58

2.66

Vdet1_A

2.40

2.48

2.56

Vdet1_B

1.99

2.06

2.13

Vdet1_C

1.90

1.96

2.02

Vdet1_D

1.80

1.86

1.92

Table 5.42

Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)

Conditions: 1.8 V

≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T

a = –40 to +105°C

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Voltage detection level

Voltage detection circuit

(LVD2)*1

Vdet2_0

2.71

2.90

3.09

V

Figure 5.52

At falling edge VCC

Vdet2_1

2.43

2.60

2.77

Vdet2_2

1.87

2.00

2.13

Vdet2_3*2

1.69

1.80

1.91

Wait time after power-on

reset cancellation

At normal startup*3

tPOR

―

9.1

―

ms

Figure 5.50

During fast startup time*4

tPOR

―

1.6

―

Wait time after voltage

monitoring 1 reset

cancellation

Power-on voltage monitoring

1 reset disabled*3

tLVD1

―

568

―μs

Figure 5.51

Power-on voltage monitoring

1 reset enabled*4

―

100

―

Wait time after voltage monitoring 2 reset cancellation

tLVD2

―

100

―μs

Figure 5.52

Response delay time

tdet

――

350

μs

Figure 5.49

Minimum VCC down time*5

tVOFF

350

――

μs

Figure 5.49,

VCC = 1.0 V or above

Power-on reset enable time

tW(POR)

1

――

ms

Figure 5.50,

VCC = below 1.0 V

LVD operation stabilization time (after LVD is enabled)

Td(E-A)

――

300

μs

Figure 5.51, Figure 5.52

Hysteresis width (LVD1 and LVD2)

VLVH

―

70

―

mV

Vdet1_4 selected

―

60

―

Vdet1_5 to 9, LVD2 selected

―

50

―

When selection is from

among Vdet1_A to B.

―

40

―

When selection is from

among Vdet1_C to D.

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