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S3A7 데이터시트(PDF) 90 Page - Renesas Technology Corp |
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S3A7 데이터시트(HTML) 90 Page - Renesas Technology Corp |
90 / 133 page R01DS0263EU0100 Rev.1.00 Page 90 of 130 Feb 23, 2016 S3A7 2. Electrical Characteristics Figure 2.70 SSI data output delay from SSIWSn change time 2.3.14 SD/MMC Host Interface Timing Figure 2.71 SD/MMC host interface signal timing Table 2.44 SD/MMC host interface signal timing Conditions: VCC = AVCC0 = 2.7 to 5.5 V Middle drive output is selected in the Drive Capavility Control in PmnPFS register Item Symbol Min Max Unit Test conditions SDCLK clock cycle tSDCYC 62.5 - ns Figure 2.71 SDCLK clock high-level pulse width tSDWH 18.25 - ns SDCLK clock low-level pulse width tSDWL 18.25 - ns SDCLK clock rising time tSDLH -10 ns SDCLK clock falling time tSDHL -10 ns SDCMD/SDDAT output data delay tSDODLY –18.25 18.25 ns SDCMD/SDDAT input data setup tSDIS 9.25 - ns SDCMD/SDDAT input data hold tSDIH 23.25 - ns tDTRW SSIWSn (Input) SSIDATAn (Output) MSB bit output delay from SSIWSn change time for Slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] SDCLK (output) SDCMD/SDDAT (input) SDCMD/SDDAT (output) tSDODLY(max) tSDIS tSDIH tSDLH tSDHL tSDCYC tSDWH tSDWL tSDODLY(min) |
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