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UPD48288118AF1 데이터시트(PDF) 32 Page - Renesas Technology Corp

부품명 UPD48288118AF1
상세설명  288M-BIT Low Latency DRAM
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48288118AF1 데이터시트(HTML) 32 Page - Renesas Technology Corp

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µµµµPD48288118AF1
R10DS0255EJ0101 Rev. 1.01
Page 32 of 51
Jan. 15, 2016
2.14 Operation with Multiplexed Address
In multiplexed address mode, the address can be provided to the
µPD48288118AF1 in two parts that are latched
into the memory with two consecutive rising clock edges. This provides the advantage that a maximum of 11 address
balls are required to control the
µPD48288118AF1, reducing the number of balls on the controller side. The data bus
efficiency in continuous burst mode is not affected for BL=4 and BL=8 since at least two clocks are required to read the
data out of the memory. The bank addresses are delivered to the
µPD48288118AF1 at the same time as the WRITE
command and the first address part, Ax.
This option is available by setting bit A5 to “1” in the mode register. Once this bit is set, the READ, WRITE, and
MRS commands follow the format described in Figure 2-26. See Figure 2-28. Power-Up Sequence in Multiplexed
Address Mode
for the power-up sequence.
Figure 2-26. Command Description in Multiplexed
Remarks 1.
Ax, Ay : Address
BA
: Bank Address
2.
The minimum setup and hold times of the two address parts are defined tAS and tAH.
CK#
CK
WE#
REF#
CS#
READ
WRITE
Don't care
MRS
Ax
Ay
Ay
Ax
Ay
Ax
BA
BA
ADDRESS
BANK
ADDRESS


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