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UPD48576118F1 데이터시트(PDF) 4 Page - Renesas Technology Corp |
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UPD48576118F1 데이터시트(HTML) 4 Page - Renesas Technology Corp |
4 / 52 page µµµµPD48576118F1 R10DS0257EJ0101 Rev. 1.01 Page 4 of 51 Jan. 15, 2016 Pin Description (1/2) Symbol Type Description CK, CK# Input Clock inputs: CK and CK# are differential clock inputs. This input clock pair registers address and control inputs on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK. CS# Input Chip select CS# enables the commands when CS# is LOW and disables them when CS# is HIGH. When the command is disabled, new commands are ignored, but internal operations continue. WE#, REF# Input WRITE command pin, Refresh command pin: WE#, REF# are sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the command to be executed. A0–A21 Input Address inputs: A0–A21 define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. A21 is reserved for address expansion. This expansion address can be treated as address input, but it does not affect the operation of the device. A22 Input Reserved for future use: These signals should be tied to VSS or leave open. BA0–BA2 Input Bank address inputs; Select to which internal bank a command is being applied. D0–D17 Input Data input: The D signals form the 18-bit input data bus. During WRITE commands, the data is referenced to both edges of DK. . . Q0–Q17 Output Data output: The Q signals form the 18-bit output data bus. During READ commands, the data is referenced to both edges of QK. . . QKx, QKx# Output Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are always free running and edge- aligned with data output from the µPD48576118F1. QKx# is ideally 180 degrees out of phase with QKx. QK0 and QK0# are aligned with Q0–Q8. QK1 and QK1# are aligned with Q9–Q17. DK, DK# Input Input data clock; DK and DK# are the differential input data clocks. All input data is referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. All Ds are referenced to DK and DK#. DM Input Input data mask; The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH along with the WRITE input data. DM is sampled on both edges of DK. The signal should be VSS if not used. QVLD Output Data valid; The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#. |
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