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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HT56RB688 데이터시트(PDF) 86 Page - Holtek Semiconductor Inc |
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HT56RB688 데이터시트(HTML) 86 Page - Holtek Semiconductor Inc |
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86 / 164 page  Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCLK, is shared with an I/O line, the required pin function is chosen via PCKEN in the SIM0CTL0 register. The Peripheral Clock function is controlled using the SIM0CTL0 register. The clock source for the Peripheral Clock Output can originate from either the Timer/Event Counter 0 overflow signal divided by two or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIM0CTL0 register is the overall on/off control, setting the bit high enables the Peripheral Clock, clearing it disables it. The required division ratio of the system clock is selected using the PCKPSC0 and PCKPSC1 bits in the same register. If the system enters the Sleep Mode, the Peripheral Clock output will be disabled. Rev. 1.10 86 April 15, 2013 HT56RB688 TinyPowerTM A/D type Smart Card OTP MCU with LCD, DAC, ISO 7816 and USB Interfaces f S Y S T i m e r / E v e n t C o u n t e r 0 o v e r f l o w s i g n a l ¸ 2 P C L K o r I / O S e l e c t P C L K o r I / O ¸ 1 , 4 , 8 P C K E N P C K P S C 0 P C K P S C 1 S l e e p M o d e Peripheral Clock Block Diagram |
유사한 부품 번호 - HT56RB688_13 |
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유사한 설명 - HT56RB688_13 |
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