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HT82K95E 데이터시트(PDF) 15 Page - Holtek Semiconductor Inc

부품명 HT82K95E
상세설명  USB Multimedia Keyboard Encoder 8-Bit MCU
Download  42 Pages
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제조업체  HOLTEK [Holtek Semiconductor Inc]
홈페이지  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

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HT82K95E/HT82K95A
Rev. 2.40
15
November 5, 2014
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 0. The internal clock
source is coming from fSYS/4.
The external clock input allows the user to count exter-
nal events, measure time intervals or pulse widths.
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 1. The internal clock
source is coming from fSYS/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths.
There are 2 registers related to the Timer/Event Counter
0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical regis-
ters are mapped to TMR0 location; writing TMR0 makes
the starting value be placed in the Timer/Event Counter
0 preload register and reading TMR0 gets the contents
of the Timer/Event Counter 0. The TMR0C is a
timer/event counter control register, which defines some
options.
There are 3 registers related to Timer/Event Counter 1;
TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H op-
erations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting en-
able or disable and active edge.
The T0M0/T0M1, T1M0/T1M1 bits define the operating
mode. The event count mode is used to count external
events, which means the clock source comes from an
external (TMR0/TMR1) pin. The timer mode functions
as a normal timer with the clock source coming from the
fSYS/4 (Timer0/Timer1). The pulse width measurement
mode can be used to count the high or low level duration
of the external signal (TMR0/TMR1). The counting is
based on the fSYS/4 (Timer0/Timer1).
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contents in the Timer/Event Counter 0/1 to FFH or
FFFFH. Once overflow occurs, the counter is reloaded
from the Timer/Event Counter 0/1 preload register and
generates the interrupt request flag (T0F/T1F; bit 5/6 of
INTC) at the same time.
In the pulse width measurement mode with the
T0ON/T1ON and TE bits equal to one, once the
TMR0/TMR1 has received a transient from low to high
(or high to low if the T0E/T1E bits is
²0²) it will start
counting until the TMR0/TMR1 returns to the original
level and resets the T0ON/T1ON. The measured result
will remain in the Timer/Event Counter 0/1 even if the
activated transient occurs again. In other words, only
one cycle measurement can be done. Until setting the
T0ON/T1ON, the cycle measurement will function again
as long as it receives further transient pulse. Note that,
in this operating mode, the Timer/Event Counter 0/1
starts counting not according to the logic level but ac-
cording to the transient edges. In the case of counter
overflows, the counter 0/1 is reloaded from the
Timer/Event Counter 0/1 preload register and issues the
interrupt request just like the other two modes. To en-
able the counting operation, the timer ON bit
(T0ON/T1ON; bit 4 of TMR0C/TMR1C) should be set to
T 0 M 1
T 0 M 0
T M R 0
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
T i m e r / E v e n t C o u n t e r 0
P r e l o a d R e g i s t e r
T i m e r / E v e n t
C o u n t e r 0
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
f S Y S / 4
Timer/Event Counter 0
T 1 M 1
T 1 M 0
T M R 1
T 1 E
T 0 M 1
T 0 M 0
T 0 O N
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
1 6 B i t s
T i m e r / E v e n t C o u n t e r
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
f S Y S / 4
1 6 B i t s
T i m e r / E v e n t C o u n t e r
( T M R 1 H / T M R 1 L )
L o w B y t e
B u f f e r
Timer/Event Counter 1


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