HT82M9BE/HT82M9BA

Rev. 1.80

16

December 22, 2008

also depends on the control register. If the control regis-

ter bit is

²1², the input will read the pad state. If the con-

trol register bit is

²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction. For output function,

CMOS/NMOS/PMOS configurations can be selected

(NMOS and PMOS are available for PA only). These

control registers are mapped to locations 13H 15H and

17H.

After a chip reset, these input/output lines remain at high

levels or in a floating state (depending on the

pull-high/low options). Each bit of these input/output

latches can be set or cleared by

²SET [m].i² and ²CLR

[m].i

² (m=12H, 14H or 16H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of PA0~PA7, PB4 and PB7 has the capability

of waking-up the device.

There are pull-high/low options available for I/O lines.

Once the pull-high/low option of an I/O line is selected,

the I/O line have pull-high/low resistor. Otherwise, the

pull-high/low resistor is absent. It should be noted that a

non-pull-high/low I/O line operating in input mode will

cause a floating state.

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

Low Voltage Reset

- LVR

The microcontroller contains a low voltage reset circuit

in order to monitor the supply voltage of the device. If the

supply voltage of the device drops to within the range of

tery, the LVR will automatically reset the device inter-

nally.

The LVR includes the following specifications:

exist for more than 1ms. If the low voltage state does

not exceed 1ms, the LVR will ignore it and will not per-

form a reset function.

²OR² function with the external

RES signal to perform a chip reset.

tion at 6MHz or 12MHz system clock.

5 . 5 V

0 . 9 V

5 . 5 V

2 . 7 V

2 . 4 V

5 . 5 V

0 . 9 V

0 V

R e s e t S i g n a l

R e s e t

* 1

* 2

N o r m a l O p e r a t i o n

R e s e t

L V R D e t e c t V o l t a g e

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

*2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.