GS8160Z18/36DGT-xxxV

18Mb Pipelined and Flow Through

Synchronous NBT SRAMs

333 MHz–150 MHz

1.8 V or 2.5 V I/O

100-Pin TQFP

Commercial Temp

Industrial Temp

Rev: 1.03a 9/2013

1/22

© 2011, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and

144Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS8160Z18/36DGT-xxxV is an 18Mbit Synchronous

Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL

or other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8160Z18/36DGT-xxxV may be configured by the user

to operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

Parameter Synopsis

-333

-250

-200

-150

Unit

Pipeline

3-1-1-1

tCycle

3.0

3.0

3.0

4.0

3.0

5.0

3.8

6.7

ns

ns

305

360

245

285

205

235

175

195

mA

mA

Flow

Through

2-1-1-1

tCycle

5.0

5.0

5.5

5.5

6.5

6.5

7.5

7.5

ns

ns

235

265

215

245

205

225

190

205

mA

mA