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DAC38RF83IAAV 데이터시트(PDF) 4 Page - Texas Instruments |
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DAC38RF83IAAV 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 155 page 4 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3C – DECEMBER 2016 – REVISED JULY 2017 www.ti.com DAC38RF83 DAC38RF93 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Changes from Revision A (February 2017) to Revision B Page • Added VDDE1 rail to Supply Voltage Range in the Absolute Maximum Ratings table........................................................ 13 • Changed subtitle From: LVDS OUTPUT: SYNC1+/-, SYNC2+/- To: LVDS OUTPUT: SYNC0+/-, SYNC1+/- in the Electrical Characteristics - Digital Specifications table ........................................................................................................ 17 • Added "0 dBFS" amplitude of input digital data in test conditions in the Electrical Characteristics - AC Specifications table ...................................................................................................................................................................................... 20 • Changed the NSD values for -9 dBFS in Electrical Characteristics - AC Specifications table ............................................ 22 • Added the PLL/VCO Electrical Characteristics table............................................................................................................ 23 • Changed From: VCO frequency = 5898.24 MHz To: VCO frequency = 5.9 GHz in Figure 43 and Figure 44 .................... 32 • Changed From: measured at 1 GHz To: measured at 1.8 GHz in Figure 41 and Figure 43............................................... 32 • Added JESD204B clock phase register setting to Table 36 ................................................................................................ 65 • Removed descriptions for CLKJESD_DIV register from Table 36 ...................................................................................... 65 • Added JESD204B clock phase register setting to Table 37................................................................................................. 65 • Added information about the DAC output total current for various full scale current settings in DAC Fullscale Output Current ................................................................................................................................................................................. 72 • Changed the text in the second sentence of the DAC Transfer Function for DAC38RF80/90/84 section ......................... 75 • Changed Bit 0 of Table 123 From: Enables the GSM PLL To: Reserved.......................................................................... 134 • Changed Table 125 ........................................................................................................................................................... 136 • Changed description of SERDES_REFCLK_DIV register field in Table 126 .................................................................... 137 • Changed Bit 12:11, 6:5 and 4:2 of Table 129 ................................................................................................................... 139 • Updated the startup sequence in Figure 167 .................................................................................................................... 141 |
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