GS81314LQ19/37GK-933/800

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02 3/2016

6/39

© 2015, GSI Technology

Initialization Summary

Prior to functional use, these devices must first be initialized and configured. The steps described below will ensure that the

internal logic has been properly reset, and that functional timing parameters have been configured appropriately.

Flow Chart

Power-Up

Reset SRAM

Training

Required?

Address / Control

Input Training

Read Data

Output Training

Write Data

Input Training

Normal Operation

Train

Again?

Yes

No

No

Yes

Enable PLL,

Wait for Lock

Additional

Wait for Calibrations

Configuration

Notes:

1. MZT[1:0] and PZT[1:0] mode pins are used to set the default ODT state of all

input groups at power-up, and whenever RST is asserted High. The ODT state

for each input group can be changed any time thereafter using Register Write

Mode to program certain bits in the Configuration Registers.

2. Calibrations are performed for driver impedance, ODT impedance, and the PLL

current source immediately after RST is de-asserted Low. The calibrations can

take up to 384K cycles total. See the Power-Up and Reset Requirements section

for more information.

3. The PLL can be enabled by the PLL pin, or by the PLL Enable (PLE) bit in the

Configuration Registers. See the PLL Operation section for more information.

4. If the PLE register bit is used to enable the PLL, then Register Write Mode will

likely have to be utilized in the “Asynchronous, Pre-Input Training” method in

order to change the state of the bit, since Address / Control Input Training has

not yet been performed. See the Configuration Registers section for more infor-

mation.

5. It can take up to 64K cycles for the PLL to lock after it has been enabled.

6. Special Loopback Modes are available in these devices to perform Address /

Control Input Training; they are selected and enabled via the Loopback Mode

Select (LBK[1:0]) and Loopback Mode Enable (LBKE) bits in the Configuration

Registers.

7. If Loopback Modes are used to perform Address / Control Input Training, then

Register Write Mode will likely have to be utilized in the “Asynchronous,

Pre-Input Training” method in order to change the states of the LBK[1:0] and

LBKE register bits.

8. Loopback Modes can also be used for Read Data Output Training, if desired.

See the Signal Timing Training and Loopback Mode sections for more informa-

tion.

9. “Additional Configuration” includes programming the Read Latency to 5 cycles

(which is required by these devices), and any other configuration changes

required by the system. Since this step is performed after Address / Control Input

Training, Register Write Mode can be utilized in the “Asynchronous, Post-Input

Training” method (or perhaps the “Synchronous” method, if the synchronous tim-

ing requirements can be met at the particular operating frequency).

10. It is up to the system to determine if/when re-training is necessary.