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CS5471-BS 데이터시트(PDF) 11 Page - Cirrus Logic |
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CS5471-BS 데이터시트(HTML) 11 Page - Cirrus Logic |
11 / 14 page CS5471 11 3. PIN DESCRIPTION Clock Generator XIN - Master Clock Input Control Pins and Serial Data I/O SE - Serial Port Enable. When SE is low, the output pins of the serial port are 3-stated. SDO - Serial Port Output. Data will be at a rate determined by SCLK. FSO - Frame Signal Output. Framing signal output for data transfer from SDO pin. SCLK - Serial Clock Output. A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined by XIN frequency and state of OWRS input pin. RESET - Reset. When reset is taken low, all internal registers are set to their default states. GAIN - Input Gain Control. Sets input gain for current channel. A logic high sets internal gain to 1, a logic low level sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor to DGND). OWRS - Output Word Rate Select. When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200K resistor to DGND). 1 2 3 4 5 6 7 813 14 15 16 17 18 19 20 9 10 11 12 Serial Clock Output SCLK VD+ Digital Supply Serial Data Output SDO DGND Digital Ground Frame Sync FSO CPD Charge Pump Drive Serial Port Enable SE XIN Master Clock Current Input Gain GAIN RESET Reset Analog Ground AGND OWRS Output Word Rate Select Reference Input VREFIN VIN+ Differential Voltage Input 1 Reference Output VREFOUT VIN- Differential Voltage Input 1 Positive Analog Supply VA+ IIN+ Differential Current Input 1 Negative Analog Supply VA- IIN- Differential Current Input 1 |
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