AD7091R-5

Data Sheet

Rev. 0 | Page 8 of 34

Pin No.

Mnemonic

Description

TSSOP

LFCSP

16

14

address for the AD7091R-5. The device address depends on the logic state of these pins.

17

15

SDA

Serial Data Input/Output. This open-drain output requires a pull-up resistor. The output coding is

straight binary for the voltage channels.

18

16

SCL

mode is compatible with both 100 kHz (standard mode) and 400 kHz (fast mode) operating

modes.

19

17

This is a multifunction pin determined by the configuration register and mode of conversion.

Convert Start Input Signal (CONVST). Edge triggered logic input. The falling edge of CONVST

places the ADC into hold mode and initiates a conversion. The logic level of CONVST at EOC

controls the power modes of the AD7091R-5.

function as a general-purpose digital output.

20

18

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the

recommended values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and

21

EPAD

Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be

soldered to GND.

1

N/A means not applicable.