4

SL1466

PIN DESCRIPTION

PIN NO

PIN NAME

DESCRIPTION

(Note units are MHz, Amps and Volts)

19

RF AGC SET

Connect to V

CC

via 1.8K resistor

20

IF GND

IF stage ground

21

IF IP

IF input (preferred input for single ended use)

22

IF IPB

IF input

23

IF V

CC

IF stage V

CC

24

VIDEO FB-

Loop amp negative input. Connected to VIDEO + via loop network

25

VIDEO-

Loop amp negative output

26

VIDEO+

Loop amp positive output

27

VIDEO FB+

Loop amp positive input. Connected to VIDEO- via loop network

28

V

CC

Chip V

CC

FUNCTIONAL DESCRIPTION

The SL1466 is a wideband PLL FM demodulator,

optimised for application in satellite receiver systems and

requiring a minimal external component count. It contains all

the elements required for the construction of a phase locked

loop circuit, with the exception of tuning components for the

local oscillator. Also included is an AFC detector circuit for

generation of error signals to correct for any frequency drift in

the outdoor unit local oscillator. A block diagram is shown in

Fig. 2 and a typical application in Fig. 6.

The internal pin connections are shown in Fig. 1.

In normal applications the second satellite IF of typically

403.2 or 479.5 MHz is fed to the RF preamplifier, which

contains a two stage level detect circuit. This generates two

AGC signals, one of which controls the gain of the internal IF

amplifier stage and one which can be used for controlling the

gain of an external RF preamplifier so maintaining a fixed level

to the input of the phase detector for optimum threshold,

performance. The typical AGC curves are shown in Fig. 4.

The output of the preamplifier is fed to the mixer section

which is of a balanced design for low radiation. In this stage the

IF signal is mixed with the local oscillator signal, which is

generated by an on board oscillator.

The oscillator is tuned internally, requiring only an external

fixed LC tank and is optimised for high linearity over the normal

deviation range. Typical frequency versus video drive voltage

response for the oscillator is shown in Fig. 8. This response

was measured with a modulated carrier. The compensated

oscillator temperature stability is typically 0.05MHz/

°C.

The gain of the oscillator is nominally Ko = 54MHz/Volt.

Note: Because there is a x3 amplifier in the video output

section, the overall chip gain (MHz/V) is one third of the VCO

gain or18MHz/Volt. The gain may be set accurately by means

of potential divider connected to Pin 10. (+4.5V)

The output of the mixer is then fed to the loop amplifier

around which feedback is applied to determine loop amplifier

transfer characteristics. The output of the loop amplifier is

referenced so as to eliminate V

CC

dependence of the VCO.

The loop amplifier drives a buffer amplifier, which can be

connected to a 75 Ohm load or a high impedance stage to give

greater linearity and approximately 6dB higher demodulated

signal. The video polarity can be inverted depending on the

sense of the video polarity select input; open circuit or a

resistor to V

CC

gives positive video whereas a resistor to V

EE

gives negative video.

R2

C1

VIDEO DRIVE

RF INPUT

VCO

R1

VCO GAIN = Ko RAD/SEC/VOLT

VIDEO

X 3

PHASE DETECTOR

GAIN = Kd VOLT/RAD

Fig. 3 Design of PLL loop parameters