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FIN3385 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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FIN3385 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page © 2004 Fairchild Semiconductor Corporation DS500864 www.fairchildsemi.com October 2003 Revised January 2004 FIN3385 • FIN3383 Low Voltage 28-Bit Flat Panel Display Link Serializers General Description The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low Voltage Differential Signaling) data streams. A phase- locked transmit clock is transmitted in parallel with the data steam over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL data are sampled and trans- mitted. These chipsets are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Features s Low power consumption s 20 MHz to 85 MHz shift clock support s ±1V common-mode range around 1.2V s Narrow bus reduces cable size and cost s High throughput (up to 2.38 Gbps throughput) s Internal PLL with no external component s Compatible with TIA/EIA-644 specification s Devices are offered in 48- and 56-lead TSSOP packages Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. TABLE 1. Display Panel Link Serializers/De-Serializers Chip Matrix Block Diagram Functional Diagram for FIN3385 and FIN3383 Order Number Package Number Package Description FIN3383MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide FIN3385MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Part CLK Frequency LVTTL IN LVDS OUT Package FIN3385 85 28 4 56 TSSOP FIN3383 66 28 4 56 TSSOP |
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