©2001 Integrated Device Technology, Inc.

JULY 2001

DSC 4830/13

1

Functional Block Diagram

Features:

x

True Dual-Port memory cells which allow simultaneous

access of the same memory location

x

High-speed clock to data access

– Commercial: 4.2/5/6ns (max.)

– Industrial: 5/6ns (max)

x

Pipelined output mode

x

Counter enable and reset features

x

Dual chip enables allow for depth expansion without

additional logic

x

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

– Fast 4.2ns clock to data out

– 1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

x

Separate byte controls for multiplexed bus and bus

matching compatibility

x

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

x

LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os and control signals on each port

x

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

x

Available in a 208-pin Plastic Quad Flatpack (PQFP) and

208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid

Array

HIGH-SPEED 3.3V 32K x 36

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70V3579S

Counter/

Address

Reg.

Counter/

Address

Reg.

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

B

W

0

L

B

W

1

L

B

W

2

L

B

W

3

L

B

W

3

R

B

W

2

R

B

W

1

R

B

W

0

R

Din_L

ADDR_L

Din_R

ADDR_R

4830 tbl 01

32K x 36

MEMORY

ARRAY

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