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TLA2024IRUGT 데이터시트(PDF) 5 Page - Texas Instruments |
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TLA2024IRUGT 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 33 page 5 TLA2021, TLA2022, TLA2024 www.ti.com SBAS846 – NOVEMBER 2017 Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See the Full-Scale Range (FSR) and LSB Size section for more information. (2) Best-fit INL; covers 99% of full-scale. (3) Includes all errors from onboard PGA and voltage reference. 7.5 Electrical Characteristics minimum and maximum specifications apply from TA = –40°C to +85°C; typical specifications are at TA = 25°C; all specifications are at VDD = 3.3 V, data rate = 128 SPS, and FSR = ±2.048 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Common-mode input impedance FSR = ±6.144 V(1) 10 MΩ FSR = ±4.096 V(1), FSR = ±2.048 V 6 FSR = ±1.024 V 3 FSR = ±0.512 V, FSR = ±0.256 V 100 Differential input impedance FSR = ±6.144 V(1) 22 MΩ FSR = ±4.096 V(1) 15 FSR = ±2.048 V 4.9 FSR = ±1.024 V 2.4 FSR = ±0.512 V, ±0.256 V 710 kΩ SYSTEM PERFORMANCE Resolution (no missing codes) 12 Bits DR Data rate 128, 250, 490, 920, 1600, 2400, 3300 SPS Data rate variation All data rates –10% 10% INL Integral nonlinearity(2) 1 LSB Offset error ±1 LSB Offset drift 0.01 LSB/°C Gain error(3) 0.05% Gain drift(3) 10 ppm/°C PSRR Power-supply rejection ratio 85 dB CMRR Common-mode rejection ratio 90 dB DIGITAL INPUT/OUTPUT VIL Logic input level, low GND 0.3 VDD V VIH Logic input level, high 0.7 VDD 5.5 V VOL Logic output level, low IOL = 3 mA GND 0.15 0.4 V Input leakage current GND < VDigital Input < VDD –10 10 µA POWER SUPPLY IVDD Supply current Power-down 0.5 µA Operating 150 PD Power dissipation VDD = 5 V 0.9 mW VDD = 3.3 V 0.5 VDD = 2 V 0.3 |
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