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AD73322 데이터시트(PDF) 20 Page - Analog Devices |
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AD73322 데이터시트(HTML) 20 Page - Analog Devices |
20 / 44 page AD73322 –19– REV. B The SPORT can work at four different serial clock (SCLK) rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8, where DMCLK is the internal or device master clock resulting from the external or pin master clock being divided by the master clock divider. SPORT Register Maps There are two register banks for each codec in the AD73322: the control register bank and the data register bank. The con- trol register bank consists of eight read/write registers, each eight bits wide. Table XII shows the control register map for the AD73322. The first two control registers, CRA and CRB, are reserved for controlling the SPORT. They hold settings for parameters such as serial clock rate, internal master clock rate, sample rate and device count. As both codecs are internally cascaded, registers CRA and CRB on each codec must be pro- grammed with the same setting to ensure correct operation (this is shown in the programming examples). The other five regis- ters; CRC through CRH are used to hold control settings for the ADC, DAC, Reference, Power Control and Gain Tap sections of the device. It is not necessary that the contents of CRC through CRH on each codec be similar. Control regis- ters are written to on the negative edge of SCLK. The data register bank consists of two 16-bit registers that are the DAC and ADC registers. Master Clock Divider The AD73322 features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to pro- duce an internal master clock signal (DMCLK) that is used to calculate the sampling and serial clock rates. The master clock divider is programmable by setting CRB:4-6. Table VIII shows the division ratio corresponding to the various bit settings. The default divider ratio is divide-by-one. Table VIII. DMCLK (Internal) Rate Divider Settings MCD2 MCD1 MCD0 DMCLK Rate 0 0 0 MCLK 0 0 1 MCLK/2 0 1 0 MCLK/3 0 1 1 MCLK/4 1 0 0 MCLK/5 1 0 1 MCLK 1 1 0 MCLK 1 1 1 MCLK Serial Clock Rate Divider The AD73322 features a programmable serial clock divider that allows users to match the serial clock (SCLK) rate of the data to that of the DSP engine or host processor. The maximum SCLK rate available is DMCLK and the other available rates are: DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK rate. The serial clock divider is programmable by setting bits CRB:2–3. Table IX shows the serial clock rate corresponding to the various bit settings. Table IX. SCLK Rate Divider Settings SCD1 SCD0 SCLK Rate 0 0 DMCLK/8 0 1 DMCLK/4 1 0 DMCLK/2 1 1 DMCLK Sample Rate Divider The AD73322 features a programmable sample rate divider that allows users flexibility in matching the codec’s ADC and DAC sample rates (decimation/interpolation rates)to the needs of the DSP software. The maximum sample rate available is DMCLK/ 256, which offers the lowest conversion group delay, while the other available rates are: DMCLK/512, DMCLK/1024 and DMCLK/2048. The slowest rate (DMCLK/2048) is the default sample rate. The sample rate divider is programmable by set- ting bits CRB:0-1. Table X shows the sample rate correspond- ing to the various bit settings. Table X. Sample Rate Divider Settings DIR1 DIR0 SCLK Rate 0 0 DMCLK/2048 0 1 DMCLK/1024 1 0 DMCLK/512 1 1 DMCLK/256 DAC Advance Register The loading of the DAC is internally synchronized with the unloading of the ADC data in each sampling interval. The de- fault DAC load event happens one SCLK cycle before the SDOFS flag is raised by the ADC data being ready. However, this DAC load position can be advanced before this time by modifying the contents of the DAC advance field in Control Register E (CRE:0–4). The field is five bits wide, allowing 31 increments of weight 1/(FS × 32); see Table XI. The sample rate FS is dependent on the setting of both the MCLK divider and the Sample Rate divider; see Tables VIII and X. In certain cir- cumstances this DAC update adjustment can reduce the group delay when the ADC and DAC are used to process data in series. Appendix C details how the DAC advance feature can be used. NOTE: The DAC advance register should not be changed while the DAC section is powered up. Table XI. DAC Timing Control DA4 DA3 DA2 DA1 DA0 Time Advance 0 0 0 000 s 0 0 0 0 1 1/(FS × 32) s 0 0 0 1 0 2/(FS × 32) s — — — ——— 1 1 1 1 0 30/(FS × 32) s 1 1 1 1 1 31/(FS × 32) s |
유사한 부품 번호 - AD73322_17 |
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유사한 설명 - AD73322_17 |
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