전자부품 데이터시트 검색엔진 |
|
AD73322LYR-REEL 데이터시트(PDF) 8 Page - Analog Devices |
|
AD73322LYR-REEL 데이터시트(HTML) 8 Page - Analog Devices |
8 / 49 page AD73322L Rev. A | Page 7 of 48 SIGNAL RANGES Table 3. Mnemoic Description Range VREFCAP 1.2 V ± 10% VREFOUT 1.2 V ± 10% ADC Maximum input range at VIN 1.578 V p-p Nominal reference level 1.0954 V p-p DAC Maximum voltage output swing Single-Ended 1.578 V p-p Differential 3.156 V p-p Nominal voltage output swing Single-Ended 1.0954 V p-p Differential 2.1909 V p-p Output bias voltage VREFOUT TIMING CHARACTERISTICS AVDD = 3 V ± 10%; DVDD = 3 V ± 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted. Table 4. Parameter Limit at TA = −40°C to +105°C Unit Description Clock Signals See Figure 2 t1 61 ns min MCLK period t2 24.4 ns min MCLK width high t3 24.4 ns min MCLK width low Serial Port See Figure 4 and Figure 5 t4 t1 ns min SCLK period t5 0.4 × t1 ns min SCLK width high t6 0.4 × t1 ns min SCLK width low t7 20 ns min SDI/SDIFS setup before SCLK low t8 0 ns min SDI/SDIFS hold after SCLK low t9 10 ns max SDOFS delay from SCLK high t10 10 ns min SDOFS hold after SCLK high t11 10 ns min SDO hold after SCLK high t12 10 ns max SDO delay from SCLK high t13 30 ns max SCLK delay from MCLK |
유사한 부품 번호 - AD73322LYR-REEL |
|
유사한 설명 - AD73322LYR-REEL |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |