전자부품 데이터시트 검색엔진 |
|
COP8782C 데이터시트(PDF) 5 Page - National Semiconductor (TI) |
|
|
COP8782C 데이터시트(HTML) 5 Page - National Semiconductor (TI) |
5 / 28 page Pin Descriptions VCC and GND are the power supply pins CKI is the clock input This can come from an external source a RC generated oscillator or a crystal (in conjunc- tion with CKO) See Oscillator description RESET is the master reset input See Reset description PORT I is an 8-bit Hi-Z input port The 28-pin device does not have a full complement of PORT I pins The unavailable pins are not terminated ie they are floating A read opera- tion for these unterminated pins will return unpredictable values The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations The unterminated PORT I pins will draw pow- er only when addressed PORT L is an 8-bit IO port PORT C is a 4-bit IO port Three memory locations are allocated for the L G and C ports one each for data register configuration register and the input pins Reading bits 4 – 7 of the C-Configuration reg- ister data register and input pins returns undefined data There are two registers associated with the L and C ports a data register and a configuration register Therefore each L and C IO bit can be individually configured under software control as shown below Config Data Ports L and C Setup 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output On the 20- and 28-pin parts it is recommended that all bits of Port C be configured as outputs to minimize current PORT G is an 8-bit port with 6 IO pins (G0 – G5) and 2 input pins (G6 G7) All eight G-pins have Schmitt Triggers on the inputs There are two registers associated with the G port a data register and a configuration register Therefore each G port bit can be individually configured under software control as shown below Config Data Port G Setup 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output Since G6 and G7 are input only pins any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded Reading the G6 and G7 configuration bits will return zeros The device will be placed in the HALT mode by writing a one to the G7 bit in the G-port data register Six pins of Port G have alternate features G0 INTR (an external interrupt) G3 TIO (timercounter inputoutput) G4 SO (MICROWIREPLUS serial data output) G5 SK (MICROWIREPLUS clock IO) G6 SI (MICROWIREPLUS serial data input) G7 CKO crystal oscillator output (selected by programming the ECON register) or HALT Restartgeneral purpose input Pins G1 and G2 currently do not have any alternate func- tions PORT D is an 8-bit output port that is preset high when RESET goes low Care must be exercised with the D2 pin operation At reset the external load on this pin must en- sure that the output voltage stay above 07 VCC to prevent the chip from entering special modes Also keep the exter- nal loading on D2 to less than 1000 pF Functional Description Figure 1 shows the block diagram of the internal architec- ture Data paths are illustrated in simplified form to depict how the various logic elements communicate with each oth- er in implementing the instruction set of the device ALU AND CPU REGISTERS The ALU can do an 8-bit addition subtraction logical or shift operation in one cycle time There are five CPU registers A is the 8-bit Accumulator register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is the 8-bit address register can be auto incremented or decremented X is the 8-bit alternate address register can be incremented or decremented SP is the 8-bit stack pointer which points to the subroutine interrupt stack in RAM The SP must be initialized with soft- ware (usually to RAM address 06F Hex with 128 bytes of on-chip RAM selected or to RAM address 02F Hex with 64 bytes of on-chip RAM selected) The SP is used with the subroutine call and return instructions and with the inter- rupts B X and SP registers are mapped into the on-chip RAM The B and X registers are used to address the on-chip RAM The SP register is used to address the stack in RAM during subroutine calls and returns PROGRAM MEMORY The device contains 4096 bytes of UV erasable or OTP EPROM memory This memory is mapped in the program memory address space from 0000 to 0FFF Hex The pro- gram memory may contain either instructions or data con- stants and is addressed by the 15-bit program counter (PC) The program memory can be indirectly read by the LAID (Load Accumulator Indirect) instruction for table lookup of constant data All locations in the EPROM program memory will contain 0FF Hex (all 1’s) after the device is erased OTP parts are shipped with all locations already erased to 0FF Hex Un- used EPROM locations should always be programmed to 00 Hex so that the software trap can be used to halt runaway program operation The device can be configured to inhibit external reads of the program memory This is done by programming the security bit in the ECON (EPROM configuration) register to zero See the ECON REGISTER section for more details DATA MEMORY The data memory address space includes on-chip RAM IO and registers Data memory is addressed directly by instructions or indirectly by means of the B X or SP point- http www nationalcom 5 |
유사한 부품 번호 - COP8782C |
|
유사한 설명 - COP8782C |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |