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SLA7060M 데이터시트(PDF) 7 Page - Allegro MicroSystems

부품명 SLA7060M
상세설명  UNIPOLAR STEPPER-MOTOR TRANSLATOR/DRIVERS
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제조업체  ALLEGRO [Allegro MicroSystems]
홈페이지  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

SLA7060M 데이터시트(HTML) 7 Page - Allegro MicroSystems

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SLA7060M THRU SLA7062M
UNIPOLAR STEPPER-MOTOR
TRANSLATOR/DRIVERS
www.allegromicro.com
7
Functional description
Device operation. These devices are complete
microstepping motor drivers with built in translator for
easy operation with minimal control lines. They are
designed to operate unipolar stepper motors in half-,
quarter-, eighth-, and sixteenth-step modes. The current in
each of the four outputs, all n-channel DMOS, is regulated
with fixed off time pulse-width modulated (PWM) control
circuitry. The current at each step is set by the value of an
external current-sense resistor (R
S), a reference voltage
(V
REF), and the DAC’s output voltage controlled by the
output of the translator.
At V
DD power up, or reset, the translator sets the DACs
to the home state (see figures for reset conditions). When
a step command signal occurs on the CLOCK input the
translator automatically sequences the DACs to the next
level (see table 2 for the current level sequence). The
microstep resolution is set by inputs M1 and M2 as shown
in table 1.
RESET input. The RESET input sets the translator to a
predefined home state (see table 2) and turns off all of the
DMOS outputs. The monitor output (MO) goes low and
all STEP inputs are ignored until the RESET input goes
low. A low-pass filter is integrated into the reset circuit;
therefore a 5 µs delay is required between the falling edge
of the RESET input and the rising edge of the CLOCK
input.
Monitor output (MO). A logic output indicator of the
initial/home state of the translator (45°). At power up the
translator is reset to the home state (phase A and phase B
output currents are both at the half-step position or
70.7%). This output is also high at the 135°, 225°, and
315° positions.
CLOCK (step) input. A low-to-high transition on the
clock input sequences the translator, which controls the
input to the DACs and advances the motor one increment.
The size of the increment is determined by the state of
inputs M1 and M2 (see table 1). The hold state is done by
stopping the CLOCK input regardless of the input level
Microstep select (M1 and M2). These logic-level
inputs set the translator step mode per table 1. Changes to
these inputs do not take effect until the rising edge of the
clock input.
Direction (CW/CCW) input. This logic-level input sets
the translator step direction. Changes to this input do not
take effect until the rising edge of the clock input.
Internal PWM current control. Each pair of outputs is
controlled by a fixed off-time (7 to 12 µs, depending on
step) PWM current-control circuit that limits the load
current to a desired value (I
TRIP). Initially, an output is
enabled and current flows through the motor winding and
R
S. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense compara-
tor resets the PWM latch, which turns off the driver for the
fixed off time during which the load inductance causes the
current to recirculate for the off time period. The driver is
then re-enabled and the cycle repeats.
Synchronous operation mode. This function pre-
vents occasional motor noise during a “hold” state, which
normally results from asynchronous PWM operation of
both motor phases. A logic high at the SYNC input is
synchronous operation; a logic low is asynchronous
operation. The use of synchronous operation during
normal stepping is not recommended because it produces
less motor torque and can cause motor vibration due to
stair-case current.
Sleep mode. Applying a voltage greater than 2 V to the
REF pin disables the outputs and puts the motor in a free
state (coast). This function is used to minimize power
consumption when not in use. Although it disables much
of the internal circuitry including the output MOSFETs
and regulator, the sequencer/translator circuit is active and
therefore a microcontroller can set the step starting point
for the next operation during the sleep mode. When
coming out of sleep mode, wait 100 µs before issuing a
step command to allow the internal circuitry to stabilize.
Table 1. Step Modes
Input
Input
M1
M2
Step Mode
H
H
Half Step
H
L
Quarter Step
L
H
Eighth Step
L
L
Sixteenth Step


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