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TC74LCX273FW 데이터시트(PDF) 4 Page - Toshiba Semiconductor

부품명 TC74LCX273FW
상세설명  Low-Voltage Octal D-Type Flip-Flop with Clear with 5-V Tolerant Inputs and Outputs
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

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TC74LCX273F/FW/FT
2002-01-11
4
Electrical Characteristics
DC Characteristics (Ta
==== ----40 to 85°C)
Characteristics
Symbol
Test Condition
VCC (V)
Min
Max
Unit
H-level
VIH
2.7 to 3.6
2.0
¾
Input voltage
L-level
VIL
2.7 to 3.6
¾
0.8
V
IOH = -100 mA
2.7 to 3.6
VCC
- 0.2
¾
IOH = -12 mA
2.7
2.2
¾
IOH = -18 mA
3.0
2.4
¾
H-level
VOH
VIN = VIH or VIL
IOH = -24 mA
3.0
2.2
¾
IOL = 100 mA
2.7 to 3.6
¾
0.2
IOL = 12 mA
2.7
¾
0.4
IOL = 16 mA
3.0
¾
0.4
Output voltage
L-level
VOL
VIN = VIH or VIL
IOL = 24 mA
3.0
¾
0.55
V
Input leakage current
IIN
VIN = 0 to 5.5 V
2.7 to 3.6
¾
±5.0
mA
Power-off leakage current
IOFF
VIN/VOUT = 5.5 V
0
¾
10.0
mA
VIN = VCC or GND
2.7 to 3.6
¾
10.0
Quiescent supply current
ICC
VIN = 3.6 to 5.5 V
2.7 to 3.6
¾
±10.0
Increase in Icc per input
DICC
VIN = VCC - 0.6 V
2.7 to 3.6
¾
500
mA
AC Characteristics (Ta
==== ----40 to 85°C)
Characteristics
Symbol
Test Condition
VCC (V)
Min
Max
Unit
2.7
¾
¾
Maximum clock frequency
fMAX
(Figure 1, Figure 2)
3.3
± 0.3
150
¾
MHz
2.7
¾
9.5
Propagation delay time (CK-Q)
tPLH
tPHL
(Figure 1, Figure 2)
3.3
± 0.3
1.5
8.5
ns
2.7
¾
9.5
Propagation delay time ( CLR -Q)
tPHL
(Figure 1, Figure 3)
3.3
± 0.3
1.5
8.5
ns
2.7
3.3
¾
Minimum pulse width (CK)
tw (H)
tw (L)
(Figure 1, Figure 2)
3.3
± 0.3
3.3
¾
ns
2.7
3.3
¾
Minimum pulse width ( CLR )
tw (L)
(Figure 3)
3.3
± 0.3
3.3
¾
ns
2.7
2.5
¾
Minimum setup time
ts
(Figure 1, Figure 2)
3.3
± 0.3
2.5
¾
ns
2.7
1.5
¾
Minimum hold time
th
(Figure 1, Figure 2)
3.3
± 0.3
1.5
¾
ns
2.7
2.5
¾
Minimum removal time
trem
(Figure 4)
3.3
± 0.3
2.0
¾
ns
2.7
¾
¾
Output to output skew
tosLH
tosHL
(Note 10)
3.3
± 0.3
¾
1.0
ns
Note 10: Parameter guaranteed by design.
(tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn|)


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