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ADE7753ARSRL 데이터시트(PDF) 5 Page - Analog Devices

부품명 ADE7753ARSRL
상세설명  Active and Apparent Energy Metering IC with di/dt sensor interface
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ADE7753
–5–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Terminology
MEASUREMENT ERROR
The error associated with the energy measurement made by
the ADE7753 is defined by the following formula:
%
Energy
True
Energy
True
ADE
by
registered
Energy
Error
Percentage
100
7753
×


=
PHASE ERROR BETWEEN CHANNELS
The digital integrator and the HPF (High Pass Filter) in
Channel 1 have non-ideal phase response. To offset this
phase response and equalize the phase response between
channels, two phase correction network is placed in Channel
1: one for the digital integrator and the other for the HPF.
Each phase correction network corrects the phase response of
the corresponding component and ensures a phase match
between Channel 1 (current) and Channel 2 (voltage) to
within ±0.1° over a range of 45Hz to 65Hz and ±0.2° over
a range 40Hz to 1kHz.
POWER SUPPLY REJECTION
This quantifies the ADE7753 measurement error as a per-
centage of reading when the power supplies are varied.
For the AC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
input signal levels when an ac (175mV rms/120Hz) signal is
introduced onto the supplies. Any error introduced by this
AC signal is expressed as a percentage of reading—see
Measurement Error definition above.
For the DC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD toAVDD . . . . . . . . . . . . . . . . . . . . .
–0.3 V
to +0.3 V
Analog Input Voltage to AGND
V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . . . . -6V to +6V
Reference Input Voltage to AGND . . . . –0.3 V to AVDD +
0.3 V
Digital Input Voltage to
DGND –0.3 V to DVDD + 0.3 V
Digital Output Voltage to
DGND –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . .
–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150°C
20 Pin SSOP, Power Dissipation . . . . . . . . . . . .
450 mW
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . .
112°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu-
late on the human body and test equipment and can discharge without detection. Although the ADE7753
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
input signal levels when the supplies are varied ±5%. Any
error introduced is again expressed as a percentage of
reading.
ADC OFFSET ERROR
This refers to the DC offset associated with the analog inputs
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see a dc analog input signal. The
magnitude of the offset depends on the gain and input range
selection - see characteristic curves. However, when HPF1 is
switched on the offset is removed from Channel 1 (current)
and the power calculation is not affected by this offset. The
offsets may be removed by performing an offset calibration -
see Analog Inputs.
GAIN ERROR
The gain error in the ADE7753 ADCs is defined as the
difference between the measured ADC output code (minus
the offset) and the ideal output code - see Channel 1 ADC &
Channel 2 ADC. It is measured for each of the input ranges
on Channel 1 (0.5V, 0.25V and 0.125V). The difference is
expressed as a percentage of the ideal code.
GAIN ERROR MATCH
The Gain Error Match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 (for each
of the input ranges) and a gain of 2, 4, 8, or 16. It is expressed
as a percentage of the output ADC code obtained under a gain
of 1. This gives the gain error observed when the gain
selection is changed from 1 to 2, 4, 8 or 16.
WARNING!
ESD SENSITIVE DEVICE


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