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M41ST87W 데이터시트(PDF) 9 Page - STMicroelectronics |
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M41ST87W 데이터시트(HTML) 9 Page - STMicroelectronics |
9 / 42 page 9/42 M41ST87Y, M41ST87W OPERATING MODES The M41ST87Y/W clock operates as a slave de- vice on the serial bus. Access is obtained by im- plementing a start condition followed by the correct slave address (D0h). The 160 bytes con- tained in the device can then be accessed sequen- tially in the following order: 00h. Tenths/Hundredths of a Second Regis- ter 01h. Seconds Register 02h. Minutes Register 03h. Century/Hours Register 04h. Day Register 05h. Date Register 06h. Month Register 07h. Year Register 08h. Control Register 09h. Watchdog Register 0Ah-0Eh. Alarm Registers 0Fh. Flag Register 10h-12h. Reserved 13h. Square Wave 14h. Tamper Register 1 15h. Tamper Register 2 16h-1Dh. Serial Number (8 bytes) 1Eh-1Fh. Reserved (2 bytes) 20h-9Fh. User RAM (128 bytes) The M41ST87Y/W clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When VCC falls below VSO, the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). For more information on Battery Storage Life refer to Application Note AN1012. 2-Wire Bus Characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi-direction- al data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: – Data transfer may be initiated only when the bus is not busy. – During data transfer, the data line must remain stable whenever the clock line is High. – Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. |
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