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SN74SSTU32864ZKER 데이터시트(PDF) 11 Page - Texas Instruments |
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SN74SSTU32864ZKER 데이터시트(HTML) 11 Page - Texas Instruments |
11 / 14 page SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT VOH IOH = –100 µA 1.7 V to 1.9 V VCC–0.2 V VOH IOH = –6 mA 1.7 V 1.2 V VOL IOL = 100 µA 1.7 V to 1.9 V 0.2 V VOL IOL = 6 mA 1.7 V 0.5 V II All inputs‡ VI = VCC or GND 1.9 V ±5 µA ICC Static standby RESET = GND IO =0 19 V 100 µA ICC Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) IO = 0 1.9 V 40 mA Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 28 µA/ MHz ICCD Dynamic operating – per each data input, 1:1 configuration RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, IO = 0 1.8 V 18 µA/ clock Dynamic operating – per each data input, 1:2 configuration C a d C s c g 50% du y cyc e, One data input switching at one-half clock frequency, 50% duty cycle 36 MHz/ D input Chip-select-enabled low-power active mode – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 27 µA/ MHz ICCDLP Chip-select-enabled low-power active mode – 1:1 configuration RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, IO = 0 1.8 V 2 µA/ clock Chip-select-enabled low-power active mode – 1:2 configuration C a d C s c g 50% du y cyc e, One data input switching at one-half clock frequency, 50% duty cycle 2 MHz/ D input Data inputs, CSR VI = VREF ± 250 mV 2.5 3 3.5 Ci CLK, CLK VICR = 0.9 V, VI(PP) = 600 mV 1.8 V 2 3 pF RESET VI = VCC or GND 2.5 † All typical values are at VCC = 1.8 V, TA = 25°C. ‡ Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Note 5) MIN MAX UNIT fclock Clock frequency 500 MHz tw Pulse duration, CLK, CLK high or low 1 ns tact Differential inputs active time (see Note 6) 10 ns tinact Differential inputs inactive time (see Note 7) 15 ns DCS before CLK ↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high 0.7 tsu Setup time DCS before CLK ↑, CLK↓, CSR low 0.5 ns DODT, DCKE, and Data before CLK ↑, CLK↓ 0.5 th Hold time DCS, DODT, DCKE, and Data after CLK ↑, CLK↓ 0.5 ns NOTES: 5. All input slew rates are 1 V/ns ±20%. 6. VREF must be held at a valid input level and data inputs must be held low for a minimum time of tact max, after RESET is taken high. 7. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. |
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