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ADN2880 데이터시트(Datasheet) 2 Page - Analog Devices

부품명 ADN2880
상세내용  3.2 Gbps, 3.3 V, Low Noise, Transimpedance Amplifier
PDF  12 Pages
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제조사  AD [Analog Devices]
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3.2 Gbps, 3.3 V, Low Noise,
Transimpedance Amplifier
ADN2880
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Bandwidth: 2.5 GHz
Optical sensitivity: −24.2 dBm1
Differential transimpedance: 4400 V/A
Power dissipation: 70 mW
Differential output swing: 260 mV p-p
Input overload current: 4.3 mA p-p
On-chip RSSI function
Low frequency cutoff: 20 kHz
On-chip PD filter: RF = 200 Ω, CF = 20 pF
Die size: 0.7 mm × 1.2 mm
APPLICATIONS
3.2 Gbps or below optical receivers
SONET/GbE/FC optical receivers
SFF-8472-compliant receivers
PIN/APD-TIA receive optical subassemblies (ROSA)
GENERAL DESCRIPTION
The ADN2880 is a 3.3 V, high gain SiGe transimpedance
amplifier (TIA). The TIA converts the small signal current of a
photo detector into differential voltage output. The ADN2880
features a 315 nA typical input-referred noise, enabling an
optical sensitivity of −24.2 dBm (0.85 A/W PIN). With a
bandwidth of 2.5 GHz, the ADN2880 allows a data rate
operation up to 3.2 Gbps. Typical power dissipation is
approximately 70 mW.
To facilitate the assembly in small form factor packages, such
as TO-46 headers, the ADN2880 provides an on-chip RC filter
(200 Ω, 20 pF) and features a 20 kHz low frequency cutoff
without using an external capacitor. An on-chip RSSI circuit,
which generates a voltage proportional to the average photo-
diode current, is also available for power monitoring and
assembly alignment.
The ADN2880 is available in die form. With a chip area of
1.2 mm × 0.7 mm, the TIA layout is specifically optimized for
TO-Can-based packages.
1 Based on 1550 nm PIN, responsivity = 0.85 A/W, ER = 9 dB, BER < 10−10.
FUNCTIONAL BLOCK DIAGRAM
1400
Ω
0.85V
20pF
50
Ω
200
Ω
50
Ω
3.3V
FILTER
IN
VCCFILTER
VCC
GND
GND
CAP
5mA
OUTB
OUT
RSSI
Figure 1.
 2 page
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ADN2880
Rev. 0 | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Electrical Specifications ................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pad Layout and Function Descriptions ..........................................5
Typical Performance Characteristics ..............................................6
Assembly Recommendations...........................................................9
Outline Dimensions ....................................................................... 12
Die Information.......................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
7/05—Revision 0: Initial Version
 3 page
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ADN2880
Rev. 0 | Page 3 of 12
ELECTRICAL SPECIFICATIONS
Minimum/maximum VCC = 3.3 V ± 0.3 V, TAMBIENT = −40°C to +95°C; typical VCC = 3.3 V, TAMBIENT = 25°C, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Bandwidth (BW)1
−3 dB
1.9
2.5
GHz
Total Input Referred RMS Noise (IRMS)
CD = 0.8 pF, dc to 2.1 GHz
315
485
nA
Total Input Referred RMS Noise (IRMS)
CD = 0.6 pF, dc to 2.1 GHz
300
nA
Small Signal Transimpedance (ZT)1
100 MHz, differential
2700
4400
6200
V/A
100 MHz, single-ended
1350
2200
3100
V/A
Low Frequency Cutoff
CAP = open, IIN = 20 μA
20
kHz
CAP = 1 nF, IIN = 20 μA
1.0
kHz
Output Return Loss
DC to 3.5 GHz, differential
−26
−20
dB
Input Overload Current
ER = 10 dB, at 95°C1
2.11
4.3
mA p-p
Maximum Differential Output Swing
IIN, P- P = 2.0 mA
170
260
375
mV p-p
Output Data Transition Time
IIN, P-P = 1.0 mA; 20% to 80% rise/fall time
60
ps
PSRR
IIN = 0 mA, <10 MHz
39
dB
Group Delay Variation
1.0 GHz to 3.0 GHz
50
ps
Transimpedance Ripple
50 MHz to 1.0 GHz, single-ended
0.93
dB
Deterministic Jitter
10 μA < IIN, P- P ≤ 100 μA, K28.5 @ 3.2 Gbps
16
ps p-p
100 μA < IIN, P- P ≤ 2.0 mA, K28.5 @ 3.2 Gbps
25
ps p-p
10 μA < IIN, P- P ≤ 2.0 mA, PRBS 231 − 1 at OC48 (FEC)
38
ps p-p
Linear Output Range
Differential, <1 dB compression
210
mV p-p
Linear Input Current Range
Single-ended, <1 dB compression
53
μA p-p
DC PERFORMANCE
Power Dissipation
IIN, AVE = 0 mA
70
110
mW
Input Voltage
Compliance voltage
0.85
V
Output Common-Mode Voltage
DC (50 Ω) terminated to VCC
VCC − 0.12
V
Output Impedance
Single-ended
50
Ω
PD FILTER Resistance
RF
200
Ω
PD FILTER Capacitance
CF
20
pF
RSSI Gain
IIN, AVE = 5 μA to 1 mA
0.85
V/mA
RSSI Offset
IIN, AVE = 10 μA
8.0
mV
RSSI Accuracy
5 μA < IIN, P- P ≤ 20 μA
±7
%
20 μA < IIN, P- P ≤ 1 mA
±3
%
1 An equivalent IIN, P-P = 13 μA current signal is applied to the TIA input. No input capacitor is applied.
 4 page
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ADN2880
Rev. 0 | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage (VCC to GND)
5 V
Maximum Voltage to All Input
and Output Signal Pins
VCC + 0.4 V
Minimum Voltage to All Input
and Output Signal Pins
GND – 0.4 V
Maximum Input Current
10 mA
Storage Temperature Range
−65°C to +125°C
Operating Ambient Temperature Range
−40°C to +95°C
Maximum Junction Temperature
125°C
Die Attach Temperature (<30 sec)
410°C
Stresses above those listed under Absolute Maximum Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
 5 page
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ADN2880
Rev. 0 | Page 5 of 12
PAD LAYOUT AND FUNCTION DESCRIPTIONS
2
3
4
5
678
9
11
12
1
13
14
15
16
17
GND
IN
TEST
FILTER
FILTER
GND
OUTB
OUT
GND
10
GND
CAP
RSSI
GND
VCC
VCC
VCCFILTER
GND
Figure 2. Pad Layout
Table 3. Pad Function Descriptions
Pad No.
Mnemonic
Pin Type1
Description
1
GND
P
Ground. (Input return.)
2
IN
AI
Current Input. Bond directly to a photodiode (PD) anode.
3
TEST
AI
Test Probe Pad. Do not connect.
4, 5
FILTER
AO
Filter Output. Pad 4 and Pad 5 are metal connected. Optional bond to a PD cathode.
6
GND
P
Ground.
7
RSSI
AO
Voltage Output. Provides average input current monitoring. If not used, connect to ground.
8
CAP
AI
Low Frequency Cutoff (LFC) Setpoint. For SONET applications, see Figure 10 and contact sales
for assembly details.
9, 10, 13, 14
GND
P
Ground. (Output return.)
11
OUTB
AO
Negative Output, CML, On-Chip 50 Ω Termination (AC or DC Termination).
12
OUT
AO
Positive Output, CML, On-Chip 50 Ω Termination (AC or DC Termination).
15
VCCFILTER
P
On-Chip Filter Supply. Connect to VCC to Enable On-Chip RC Filter (200 Ω, 20 pF). Leave
unconnected if not used.
16, 17
VCC
P
3.3 V Supply. Place a 200 pF, RF decoupling capacitor close to the power pad to reduce
the power noise.
1 P = power; AI = analog input; and AO = analog output.
 6 page
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ADN2880
Rev. 0 | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (Hz)
100G
10M
100M
1G
10G
70
60
65
55
50
45
40
35
30
25
Q OUTPUT
QB OUTPUT
Figure 3. Single-Ended Transimpedance vs. Frequency
TEMPERATURE (°C)
100
–40
–200
20
406080
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.0V
3.3V
3.6V
Figure 4. Differential Transimpedance vs. VCC and Temperature
IINPP (μA)
100
0
102030
5060
40
70
80
90
5.5
5.0
4.5
4.0
3.5
2.5
3.0
2.0
Figure 5. Differential Transimpedance vs. Input Current
TEMPERATURE (°C)
100
–40
0
40
80
–20
20
60
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.0V
3.3V
3.6V
Figure 6. Bandwidth vs. VCC and Temperature
TEMPERATURE (°C)
100
–40
0
40
80
–20
20
60
90
85
80
75
70
65
60
55
50
3.0V
3.3V
3.6V
Figure 7. Power Dissipation vs. VCC and Temperature
FREQUENCY (Hz)
4G
10M
100M
1G
–20
–25
–30
–40
–35
–45
–50
Figure 8. SDD22 vs. Frequency up to 3.5 GHz, CAP = Open
 7 page
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ADN2880
Rev. 0 | Page 7 of 12
INPUT CURRENT (
μA)
1,000
10
100
1,000
100
10
1
CAP = OPEN
CAP = 1nF
Figure 9. Low Frequency Cutoff vs. Input Current
EXTERNAL CAPACITANCE AT CAP (pF)
10,000
1
10
100
1,000
18
16
14
12
10
8
6
4
2
0
Figure 10. Low Frequency Cutoff vs. Capacitance at CAP
IIN (μA)
35
05
15
10
20
25
30
30
25
20
15
10
5
0
Figure 11. RSSI Voltage Output vs. Input Current (0 μA to 35 μA)
IIN (mA)
5
01
234
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 12. Full-Scale of RSSI Voltage Output vs. Input Current
TEMPERATURE (°C)
95
–40
–10
–25
20
5
3550
6580
350
330
340
300
310
320
280
290
270
260
250
350
Figure 13. Input Noise vs. Temperature with 2 GHz Low-Pass Filter
PHOTODIODE CAPACITANCE (pF)
1.0
0
0.2
0.4
0.6
0.8
350
325
300
275
250
Figure 14. Input Referred Noise (DC to 2.0 GHz) vs.
Photodiode Capacitance CD (pF)
 8 page
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ADN2880
Rev. 0 | Page 8 of 12
52.9ps/DIV
OPTICAL POWER –22.7dBm
Figure 15. Output Eye at 3.2 Gbps with BER <10−10 (Based on a 1550 nm PIN,
Responsivity = 0.91 A/W, ER = 9 dB, PRBS 231)
FREQUENCY (GHz)
4
012
3
50
25
–25
0
–50
Figure 16. Group Delay vs. Frequency
TEMPERATURE (°C)
95
–40
–10
5
–25
20
35506580
5.5
5.0
4.5
4.0
3.5
3.0
Figure 17. Input Overload Current vs. Temperature
 9 page
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ADN2880
Rev. 0 | Page 9 of 12
ASSEMBLY RECOMMENDATIONS
Coplanar PIN Photodiode for SDH/SONET
CB
CA
VCC
OUTB
OUT
CPD
VPD
Figure 18. 5-Pin TO-46 with External Photodiode Supply VPD
Connected Through the FILTER Pin
CPD
FILTER
IN
VPD
B.W.
B.W.
B.W.
B.W.
0.85V
20pF
50
Ω
200
Ω
50
Ω
VCC
CB
VCC
GND
GND
CAP
OUTB
OUT
RSSI
B.W
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
Figure 19. Equivalent Circuit of the Assembly Including Bond Wires
Dual Planar PIN/APD Photodiode for SDH/SONET
CB
CA
VCC
OUTB
OUT
CPD
PD
VPD
Figure 20. 5-Pin TO-46 with External Photodiode Supply VPD to
a Dual Planar PIN or APD
0.85V
20pF
50
Ω
200
Ω
50
Ω
VCC
CB
CPD
IN
VCC
GND
GND
CAP
OUTB
OUT
RSSI
VPD
B.W
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
Figure 21. For Dual Planar PDs, No Connection to FILTER Pin
Table 4. Bill of Materials (BOM)
Component
Description
PD
1× vendor specific, 2.5 Gbps, photodiode
TIA
1× ADN2880 (0.7 mm × 1.2 mm), 3.2 Gbps,
transimpedance amplifier
CB
1× 200 pF, RF single-layer capacitor
CPD
1× 560 pF, RF single-layer capacitor
CA
1× 1000 pF, ceramic capacitor (optional for SDH)
Notes
One mil thickness, gold wire, ball bond recommended.
Minimize all GND bond-wire lengths.
Minimize IN, FILTER, OUT, and OUTB bond-wire lengths.
Maintain symmetry in length and orientation between OUT
and OUTB bond wires.
Maintain symmetry in length and orientation between IN and
FILTER bond wires.
Maintain symmetry between IN/FILTER and OUT/OUTB
bond wires.
 10 page
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ADN2880
Rev. 0 | Page 10 of 12
PIN Photodiode for a Non-SDH/SONET Application
CB
VCC
OUTB
OUT
SC
RSSI
Figure 22. Coplanar PIN and RSSI Layout for a 5-Pin TO-46
0.85V
20pF
50
Ω
200
Ω
50
Ω
VCC
CB
FILTER
IN
VCC
VCCFILTER
GND
GND
CAP
OUTB
OUT
RSSI
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
B.W.
Figure 23. Equivalent Circuit with Bond Wires, as Shown in Figure 22
CB
VCC
OUTB
OUT
SC
RSSI
Figure 24. Dual Planar PIN and RSSI Layout for a 5-Pin TO-46
ADN2880
PD
CB
SC
Figure 25. Side View of the Assembly, as Shown in Figure 22
Table 5. Bill of Materials (BOM)
Component
Description
PD
1× vendor specific, 2.5 Gbps, photodiode
TIA
1× ADN2880 (0.7 mm × 1.2 mm), 3.2 Gbps,
transimpedance amplifier
CB
1× 200 pF, RF single-layer capacitor
Sc
1× ceramic standoff or 1× optional capacitor
Notes
One mil thickness, gold wire, ball bond recommended.
Minimize all GND bond-wire lengths.
Minimize IN, FILTER, OUT, and OUTB bond-wire lengths.
Maintain symmetry in length and orientation between OUT
and OUTB bond wires.
Maintain symmetry in length and orientation between IN and
FILTER bond wires.
Maintain symmetry between IN/FILTER and OUT/OUTB
bond wires.




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