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LM833_05 데이터시트(Datasheet) 5 Page - ON Semiconductor

부품명 LM833_05
상세내용  Low Noise, Audio Dual Operational Amplifier
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제조사  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 5
1
Publication Order Number:
LM833/D
LM833
Low Noise, Audio Dual
Operational Amplifier
The LM833 is a standard low−cost monolithic dual general−purpose
operational amplifier employing Bipolar technology with innovative
high−performance concepts for audio systems applications. With high
frequency PNP transistors, the LM833 offers low voltage noise
(4.5 nV/ Hz ), 15 MHz gain bandwidth product, 7.0 V/
ms slew rate,
0.3 mV input offset voltage with 2.0
mV/°C temperature coefficient of
input offset voltage. The LM833 output stage exhibits no dead−band
crossover distortion, large output voltage swing, excellent phase and
gain margins, low open loop high frequency output impedance and
symmetrical source/sink AC frequency response.
For an improved performance dual/quad version, see the MC33079
family.
Features
Low Voltage Noise: 4.5 nV/ Hz
High Gain Bandwidth Product: 15 MHz
High Slew Rate: 7.0 V/ms
Low Input Offset Voltage: 0.3 mV
Low T.C. of Input Offset Voltage: 2.0 mV/°C
Low Distortion: 0.002%
Excellent Frequency Stability
Dual Supply Operation
Pb−Free Packages are Available
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage (VCC to VEE)
VS
+36
V
Input Differential Voltage Range (Note 1)
VIDR
30
V
Input Voltage Range (Note 1)
VIR
±15
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
−60 to +150
°C
ESD Protection at any Pin
− Human Body Model
− Machine Model
Vesd
600
200
V
Maximum Power Dissipation (Notes 2 and 3)
PD
500
mW
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction
temperature (TJ) is not exceeded (see power dissipation performance
characteristic).
3. Maximum value at TA ≤ 85°C.
PDIP−8
N SUFFIX
CASE 626
1
SOIC−8
D SUFFIX
CASE 751
1
MARKING
DIAGRAMS
LM833
= Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
2
(Top View)
1
3
4
8
7
6
5
Output 1
Inputs 1
Output 2
Inputs 2
VEE
VCC
1
2
1
8
LM833N
AWL
YYWWG
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
LM833
ALYW
G
1
LM833N = Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
 2 page
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LM833
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2
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Offset Voltage (RS = 10 W, VO = 0 V)
VIO
0.3
5.0
mV
Average Temperature Coefficient of Input Offset Voltage
RS = 10 W, VO = 0 V, TA = Tlow to Thigh
DVIO/DT
2.0
mV/°C
Input Offset Current (VCM = 0 V, VO = 0 V)
IIO
10
200
nA
Input Bias Current (VCM = 0 V, VO = 0 V)
IIB
300
1000
nA
Common Mode Input Voltage Range
VICR
−12
+14
−14
+12
V
Large Signal Voltage Gain (RL = 2.0 kW, VO = ±10 V)
AVOL
90
110
dB
Output Voltage Swing:
RL = 2.0 kW, VID = 1.0 V
RL = 2.0 kW, VID = 1.0 V
RL = 10 kW, VID = 1.0 V
RL = 10 kW, VID = 1.0 V
VO+
VO−
VO+
VO−
10
12
13.7
−14.1
13.9
−14.7
−10
−12
V
Common Mode Rejection (Vin = ±12 V)
CMR
80
100
dB
Power Supply Rejection (VS = 15 V to 5.0 V, −15 V to −5.0 V)
PSR
80
115
dB
Power Supply Current (VO = 0 V, Both Amplifiers)
ID
4.0
8.0
mA
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, AV = +1.0)
SR
5.0
7.0
V/
ms
Gain Bandwidth Product (f = 100 kHz)
GBW
10
15
MHz
Unity Gain Frequency (Open Loop)
fU
9.0
MHz
Unity Gain Phase Margin (Open Loop)
qm
60
°
Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz)
en
4.5
nV
Hz
Equivalent Input Noise Current (f = 1.0 kHz)
in
0.5
pA
Hz
Power Bandwidth (VO = 27 Vpp, RL = 2.0 kW, THD ≤ 1.0%)
BWP
120
kHz
Distortion (RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)
THD
0.002
%
Channel Separation (f = 20 Hz to 20 kHz)
CS
−120
dB
Figure 1. Maximum Power Dissipation
versus Temperature
Figure 2. Input Bias Current versus Temperature
TA, AMBIENT TEMPERATURE (°C)
800
600
400
200
0
−50
0
50
100
150
1000
800
600
400
200
0
−55
−25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
VCC = +15 V
VEE = −15 V
VCM = 0 V
 3 page
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LM833
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3
TA, AMBIENT TEMPERATURE (°C)
20
15
10
5.0
0
−25
0
25
50
75
100
125
−55
VCC = +15 V
VEE = −15 V
f = 100 kHz
Figure 3. Input Bias Current versus
Supply Voltage
Figure 4. Supply Current versus
Supply Voltage
Figure 5. DC Voltage Gain
versus Temperature
Figure 6. DC Voltage Gain versus
Supply Voltage
Figure 7. Open Loop Voltage Gain and
Phase versus Frequency
Figure 8. Gain Bandwidth Product
versus Temperature
TA, AMBIENT TEMPERATURE (°C)
VCC, |VEE|, SUPPLY VOLTAGE (V)
f, FREQUENCY (Hz)
VCC, |VEE|, SUPPLY VOLTAGE (V)
VCC, |VEE|, SUPPLY VOLTAGE (V)
800
600
400
200
0
5.0
10
15
20
10
8.0
6.0
4.0
2.0
0
110
105
100
95
90
−55
−25
0
25
50
75
100
125
110
100
90
80
0
5.0
10
15
20
120
100
80
60
40
20
0
1.0
10
100
1.0 k
10 k
100 k
1.0 M
10 M
0
45
90
135
180
5.0
10
15
20
RL = ∞
TA = 25°C
VCC
VO
VEE
IS
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
TA = 25°C
Phase
Gain
+
RL = 2.0 kW
TA = 25°C
TA = 25°C
 4 page
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LM833
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4
Figure 9. Gain Bandwidth Product versus
Supply Voltage
Figure 10. Slew Rate versus Temperature
Figure 11. Slew Rate versus Supply Voltage
Figure 12. Output Voltage versus Frequency
Figure 13. Maximum Output Voltage
versus Supply Voltage
Figure 14. Output Saturation Voltage
versus Temperature
TA, AMBIENT TEMPERATURE (°C)
VCC, |VEE|, SUPPLY VOLTAGE (V)
f, FREQUENCY (Hz)
VCC, |VEE|, SUPPLY VOLTAGE (V)
VCC, |VEE|, SUPPLY VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
30
20
10
0
5.0
10
15
20
10
8.0
6.0
4.0
2.0
−55
−25
0
25
50
75
100
125
10
8.0
6.0
4.0
2.0
0
35
30
25
20
15
10
5.0
0
10
100
1.0 k
10 k
1.0 M
10 M
100 k
20
15
10
5.0
0
−5.0
−10
−15
−20
15
14
13
5.0
10
15
20
5.0
10
15
20
−55
−25
0
25
50
75
100
125
f = 100 kHz
TA = 25°C
RL = 2.0k W
AV = +1.0
TA = 25°C
Vin
VO
RL
VO
VO +
RL = 10 kW
TA = 25°C
+Vsat
−Vsat
VCC = +15 V
VEE = −15 V
RL = 10 kW
+
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
AV = +1.0
Vin
VO
RL
+
Falling
Rising
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
THD
v 1.0%
TA = 25°C
Falling
Rising
 5 page
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LM833
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5
f, FREQUENCY (Hz)
2.0
1.0
0.7
0.5
0.4
0.3
0.2
10
100
1.0 k
10 k
100 k
Figure 15. Power Supply Rejection
versus Frequency
Figure 16. Common Mode Rejection
versus Frequency
Figure 17. Total Harmonic Distortion
versus Frequency
Figure 18. Input Referred Noise Voltage
versus Frequency
Figure 19. Input Referred Noise Current
versus Frequency
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
RS, SOURCE RESISTANCE (W)
140
120
100
80
60
40
20
0
100
1.0 k
10 k
100 k
1.0 M
10 M
1.0
0.1
0.01
0.001
10
5.0
2.0
1.0
100
10
1.0
10
100
1.0 k
10 k
100 k
1.0
10
100
1.0 k
10 k
100 k
1.0 M
140
120
100
80
60
40
20
160
100
1.0 k
10 k
100 k
1.0 M
10 M
10
100
1.0 k
10 k
100 k
VCC = +15 V
VEE = −15 V
TA = 25°C
−PSR
DVCM
DV0
× ADM
ADM
+
DVCM
DVO
CMR = 20 Log
VO
RL
+
+PSR = 20 Log
−PSR = 20 Log
DVEE
DVO/ADM
()
DVCC
DVO/ADM
()
+PSR
DVCC
ADM
+
DVEE
DVO
Figure 20. Input Referred Noise Voltage
versus Source Resistance
VCC = +15 V
VEE = −15 V
Vn(total) = (inRS)2 +en2 +
TA = 25°C
4KTRS
VCC = +15 V
VEE = −15 V
VCM = 0 V
DVCM = ±1.5 V
TA = 25°C
VCC = +15 V
VEE = −15 V
RS = 100 W
TA = 25°C
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
TA = 25°C
VCC = +15 V
VEE = −15 V
TA = 25°C
VO = 1.0 Vrms
VO = 3.0 Vrms
 6 page
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LM833
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6
Figure 21. Inverting Amplifier
Figure 22. Noninverting Amplifier Slew Rate
Figure 23. Noninverting Amplifier Overshoot
t, TIME (2.0
ms/DIV)
t, TIME (2.0
ms/DIV)
t, TIME (200 ns/DIV)
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
CL = 0 pF
AV = −1.0
TA = 25°C
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
CL = 0 pF
AV = +1.0
TA = 25°C
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
CL = 0 pF
AV = +1.0
TA = 25°C
ORDERING INFORMATION
Device
Package
Shipping
LM833N
PDIP−8
50 Units / Rail
LM833NG
PDIP−8
(Pb−Free)
LM833D
SOIC−8
98 Units / Rail
LM833DG
SOIC−8
(Pb−Free)
LM833DR2
SOIC−8
2500 / Tape & Reel
LM833DR2G
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
 7 page
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LM833
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7
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010)
Z
S
X S
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
 8 page
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LM833
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8
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
5
8
F
NOTE 2
−A−
−B−
−T−
SEATING
PLANE
H
J
G
D
K
N
C
L
M
M
A
M
0.13 (0.005)
B M
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.40
10.16
0.370
0.400
B
6.10
6.60
0.240
0.260
C
3.94
4.45
0.155
0.175
D
0.38
0.51
0.015
0.020
F
1.02
1.78
0.040
0.070
G
2.54 BSC
0.100 BSC
H
0.76
1.27
0.030
0.050
J
0.20
0.30
0.008
0.012
K
2.92
3.43
0.115
0.135
L
7.62 BSC
0.300 BSC
M
−−−
10
−−−
10
N
0.76
1.01
0.030
0.040
__
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
LM833/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.




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