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IRFR3707ZCPBF 데이터시트(Datasheet) 5 Page - International Rectifier

부품명 IRFR3707ZCPBF
상세내용  HEXFET Power MOSFET
PDF  11 Pages
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제조사  IRF [International Rectifier]
홈페이지  http://www.irf.com
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 1 page
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1
06/22/06
IRFR3707ZCPbF
IRFU3707ZCPbF
HEXFET® Power MOSFET
Notes
 through … are on page 11
Applications
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l Lead-Free
I-Pak
IRFU3707ZCPbF
D-Pak
IRFR3707ZCPbF
VDSS RDS(on) max Qg
30V
9.5m
:
9.6nC
Absolute Maximum Ratings
Parameter
Units
VDS
Drain-to-Source Voltage
V
VGS
Gate-to-Source Voltage
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
IDM
Pulsed Drain Current
™
PD @TC = 25°C
Maximum Power Dissipation
W
PD @TC = 100°C Maximum Power Dissipation
Linear Derating Factor
W/°C
TJ
Operating Junction and
°C
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Thermal Resistance
Parameter
Typ.
Max.
Units
RθJC
Junction-to-Case
–––
3.0
°C/W
RθJA
Junction-to-Ambient (PCB Mount)
–––
50
RθJA
Junction-to-Ambient
–––
110
300 (1.6mm from case)
-55 to + 175
50
0.33
25
Max.
56
f
39
f
220
± 20
30
PD - 96045
 2 page
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IRFR/U3707ZCPbF
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S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
–––
V
∆ΒV
DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.023
–––
V/°C
RDS(on)
Static Drain-to-Source On-Resistance
–––
7.5
9.5
m
–––
10
12.5
VGS(th)
Gate Threshold Voltage
1.35
1.80
2.25
V
∆V
GS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-5.0
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
–––
–––
150
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
71
–––
–––
S
Qg
Total Gate Charge
–––
9.6
14
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.6
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.90
–––
nC
Qgd
Gate-to-Drain Charge
–––
3.5
–––
Qgodr
Gate Charge Overdrive
–––
2.6
–––
See Fig. 16
Qsw
Switch Charge (Qgs2 + Qgd)
–––
4.4
–––
Qoss
Output Charge
–––
5.8
–––
nC
td(on)
Turn-On Delay Time
–––
8.0
–––
tr
Rise Time
–––
11
–––
td(off)
Turn-Off Delay Time
–––
12
–––
ns
tf
Fall Time
–––
3.3
–––
Ciss
Input Capacitance
–––
1150
–––
Coss
Output Capacitance
–––
260
–––
pF
Crss
Reverse Transfer Capacitance
–––
120
–––
Avalanche Characteristics
Parameter
Units
EAS
Single Pulse Avalanche Energy
d
mJ
IAR
Avalanche Current
Ù
A
EAR
Repetitive Avalanche Energy
™
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
56
f
(Body Diode)
A
ISM
Pulsed Source Current
–––
–––
220
(Body Diode)
Ù
VSD
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
2538ns
Qrr
Reverse Recovery Charge
–––
17
26
nC
ton
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
MOSFET symbol
VGS = 4.5V, ID = 12A
e
–––
VGS = 4.5V
Typ.
–––
–––
ID = 12A
VGS = 0V
VDS = 15V
TJ = 25°C, IF = 12A, VDD = 15V
di/dt = 100A/µs
e
TJ = 25°C, IS = 12A, VGS = 0V e
showing the
integral reverse
p-n junction diode.
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
Clamped Inductive Load
VDS = 15V, ID = 12A
VDS = 15V, VGS = 0V
VDD = 16V, VGS = 4.5V
e
ID = 12A
VDS = 15V
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 15A
e
VGS = 20V
VGS = -20V
Conditions
5.0
Max.
42
12
ƒ = 1.0MHz
 3 page
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3
Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
VDS, Drain-to-Source Voltage (V)
0.001
0.01
0.1
1
10
100
1000
10000
2.2V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP
10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.5V
BOTTOM
2.2V
0.1
1
10
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
2.2V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP
10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.5V
BOTTOM
2.2V
0
2
4
6
8
VGS, Gate-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
TJ = 25°C
TJ = 175°C
VDS = 10V
20µs PULSE WIDTH
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
ID = 30A
VGS = 10V
 4 page
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0246
8
10
12
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VDS= 24V
VDS= 15V
ID= 12A
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
TJ = 25°C
TJ = 175°C
VGS = 0V
0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
 5 page
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5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
10
20
30
40
50
60
Limited By Package
-75 -50 -25
0
25
50
75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
ID = 250µA
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τi (sec)
0.823
0.000128
1.698
0.000845
0.481
0.016503
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
τ
C
Ci=
τi/Ri
Ci=
τi/Ri
 6 page
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IRFR/U3707ZCPbF
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D.U.T.
VDS
ID
IG
3mA
VGS
.3
µF
50K
.2
µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V(BR)DSS
IAS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
RG
IAS
0.01
tp
D.U.T
L
VDS
+
-
VDD
DRIVER
A
15V
20V
VGS
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
160
180
200
ID
TOP
3.7A
5.6A
BOTTOM 12A
 7 page
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7
Fig 15.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode
Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D =
P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
ƒ
„
‚
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T

Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
 8 page
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8
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P
loss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =
I
rms
2
× R
ds(on )
()
+ I ×
Q
gd
i
g
× V
in × f
⎟ + I ×
Q
gs 2
i
g
× V
in × f
+ Q
g × Vg × f
()
+
Q
oss
2
×V
in × f
This simplified loss equation includes the terms Q
gs2
and Q
oss which are new to Power MOSFET data sheets.
Q
gs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1 and Qgs2, can be seen from
Fig 16.
Q
gs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to I
dmax at which time the drain voltage be-
gins to change. Minimizing Q
gs2 is a critical factor in
reducing switching losses in Q1.
Q
oss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s C
ds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss = Pconduction + Pdrive + Poutput
*
P
loss =
I
rms
2 × R
ds(on)
()
+ Q
g × Vg × f
()
+
Q
oss
2
× V
in × f
+ Q
rr × Vin × f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R
ds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss and re-
verse recovery charge Q
rr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Q
oss Characteristic
 9 page
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9
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
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IRFR/U3707ZCPbF
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I-Pak (TO-251AA) Part Marking Information
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

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