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IRF8910PBF 데이터시트(Datasheet) 5 Page - International Rectifier

부품명 IRF8910PBF
상세내용  HEXFET Power MOSFET
PDF  10 Pages
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제조사  IRF [International Rectifier]
홈페이지  http://www.irf.com
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 1 page
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1
8/11/04
IRF8910PbF
HEXFET® Power MOSFET
Notes
 through … are on page 10
SO-8
PD -95673
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l 20V VGS Max. Gate Rating
Absolute Maximum Ratings
Parameter
Units
VDS
Drain-to-Source Voltage
V
VGS
Gate-to-Source Voltage
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
ID @ TA = 70°C
Continuous Drain Current, VGS @ 10V
A
IDM
Pulsed Drain Current
c
PD @TA = 25°C
Power Dissipation
W
PD @TA = 70°C
Power Dissipation
Linear Derating Factor
W/°C
TJ
Operating Junction and
°C
TSTG
Storage Temperature Range
Thermal Resistance
Parameter
Typ.
Max.
Units
RθJL
Junction-to-Drain Lead
–––
20
°C/W
RθJA
Junction-to-Ambient
fg
–––
62.5
Max.
10
8.3
82
± 20
20
-55 to + 150
2.0
0.016
1.3
D1
D1
D2
D2
G1
S2
G2
S1
Top View
8
1
2
3
4
5
6
7
Applications
l Dual SO-8 MOSFET for POL
converters in desktop, servers,
graphics cards, game consoles
and set-top box
l Lead-Free
VDSS
RDS(on) max
ID
20V
13.4m:@VGS = 10V 10A
 2 page
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2
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S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
20
–––
–––
V
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.015
–––
V/°C
RDS(on)
Static Drain-to-Source On-Resistance
–––
10.7
13.4
m
–––
14.6
18.3
VGS(th)
Gate Threshold Voltage
1.65
–––
2.55
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-4.8
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
–––
–––
150
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
24
–––
–––
S
Qg
Total Gate Charge
–––
7.4
11
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.4
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.80
–––
nC
Qgd
Gate-to-Drain Charge
–––
2.5
–––
Qgodr
Gate Charge Overdrive
–––
1.7
–––
See Fig. 6
Qsw
Switch Charge (Qgs2 + Qgd)
–––
3.3
–––
Qoss
Output Charge
–––
4.4
–––
nC
td(on)
Turn-On Delay Time
–––
6.2
–––
tr
Rise Time
–––10–––
ns
td(off)
Turn-Off Delay Time
–––
9.7
–––
tf
Fall Time
–––
4.1
–––
Ciss
Input Capacitance
–––
960
–––
Coss
Output Capacitance
–––
300
–––
pF
Crss
Reverse Transfer Capacitance
–––
160
–––
Avalanche Characteristics
Parameter
Units
EAS
Single Pulse Avalanche Energy
d
mJ
IAR
Avalanche Current
™
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
2.5
(Body Diode)
A
ISM
Pulsed Source Current
–––
–––
82
(Body Diode)
Ù
VSD
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
17
26
ns
Qrr
Reverse Recovery Charge
–––
6.5
9.7
nC
–––
ID = 8.2A
VGS = 0V
VDS = 10V
VGS = 4.5V, ID = 8.0A
e
VGS = 4.5V
Typ.
–––
VDS = VGS, ID = 250µA
Clamped Inductive Load
VDS = 10V, ID = 8.2A
VDS = 16V, VGS = 0V, TJ = 125°C
TJ = 25°C, IF = 8.2A, VDD = 10V
di/dt = 100A/µs
e
TJ = 25°C, IS = 8.2A, VGS = 0V e
showing the
integral reverse
p-n junction diode.
MOSFET symbol
VDS = 10V, VGS = 0V
VDD = 10V, VGS = 4.5V
ID = 8.2A
VDS = 10V
VGS = 20V
VGS = -20V
VDS = 16V, VGS = 0V
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 10A e
Conditions
Max.
19
8.2
ƒ = 1.0MHz
 3 page
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3
Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
VGS
TOP
10V
8.0V
5.5V
4.5V
3.5V
3.0V
2.8V
BOTTOM
2.5V
≤60µs PULSE WIDTH
Tj = 25°C
2.5V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
2.5V
≤60µs PULSE WIDTH
Tj = 150°C
VGS
TOP
10V
8.0V
5.5V
4.5V
3.5V
3.0V
2.8V
BOTTOM
2.5V
1
2
3
4
5
6
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
TJ = 25°C
TJ = 150°C
VDS = 10V
≤60µs PULSE WIDTH
-60 -40 -20
0
20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
ID = 10A
VGS = 10V
 4 page
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4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
012345
6789
10
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VDS= 16V
VDS= 10V
ID= 8.2A
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
0.01
0.10
1.00
10.00
100.00
TJ = 25°C
TJ = 150°C
VGS = 0V
0
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
TA = 25°C
Tj = 150°C
Single Pulse
 5 page
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5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current vs.
Ambient Temperature
Fig 10. Threshold Voltage vs. Temperature
25
50
75
100
125
150
TA , Ambient Temperature (°C)
0
1
2
3
4
5
6
7
8
9
10
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
Ci=
τi/Ri
Ci=
τi/Ri
τ
4
τ
4
R
4
R
4
τ
C
τ
C
τ
5
τ
5
R
5
R
5
Ri (°C/W)
τi (sec)
1.2647
0.000091
2.0415
0.000776
18.970
0.188739
23.415
0.757700
16.803
25.10000
-75
-50
-25
0
25
50
75
100 125 150
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
ID = 250µA
 6 page
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IRF8910PbF
6
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Fig 13. Maximum Avalanche Energy
vs. Drain Current
Fig 16. Switching Time Test Circuit
Fig 17. Switching Time Waveforms
Fig 12. On-Resistance vs. Gate Voltage
D.U.T.
VDS
ID
IG
3mA
VGS
.3
µF
50K
.2
µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 15. Gate Charge Test Circuit
Fig 14. Unclamped Inductive Test Circuit
and Waveform
tp
V(BR)DSS
IAS
RG
IAS
0.01Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
VGS
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
10
20
30
40
50
60
70
80
ID
TOP
3.4A
4.9A
BOTTOM 8.2A
3
4
5
6
7
8
9
10
VGS, Gate -to -Source Voltage (V)
0.00
10.00
20.00
30.00
40.00
ID = 10A
TJ = 125°C
TJ = 25°C
 7 page
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IRF8910PbF
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7
Fig 15.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode
Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D =
P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
ƒ
„
‚
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T

Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
 8 page
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IRF8910PbF
8
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P
loss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss = Irms
2 × R
ds(on )
()
+ I ×
Q
gd
i
g
× V
in × f
⎟ + I ×
Q
gs 2
i
g
× V
in × f
+ Q
g × Vg × f
()
+
Q
oss
2
×V
in × f
This simplified loss equation includes the terms Q
gs2
and Q
oss which are new to Power MOSFET data sheets.
Q
gs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1 and Qgs2, can be seen from
Fig 16.
Q
gs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to I
dmax at which time the drain voltage be-
gins to change. Minimizing Q
gs2 is a critical factor in
reducing switching losses in Q1.
Q
oss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s C
ds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss = Pconduction + Pdrive + Poutput
*
P
loss = Irms
2 × R
ds(on)
()
+ Q
g × Vg × f
()
+ Qoss
2
× V
in × f
+ Q
rr × Vin × f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R
ds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss and re-
verse recovery charge Q
rr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Q
oss Characteristic
 9 page
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IRF8910PbF
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9
SO-8 Package Outline
Dimensions are shown in milimeters (inches)
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN
MAX
MILLIMETERS
INCHES
MIN
MAX
DIM
e
c
.0075
.0098
0.19
0.25
.025 BASIC
0.635 BAS IC
87
5
65
D
B
E
A
e
6X
H
0.25 [.010]
A
6
7
K x 45°
8X L
8X c
y
0.25 [.010]
CA B
e1
A
A1
8X b
C
0.10 [.004]
4
3
12
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
ASUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
8X 1.78 [.070]
SO-8 Part Marking Information (Lead-Free)
DATE CODE (YWW)
XXXX
INTERNATIONAL
RECTIFIER
LOGO
F7101
Y = LAST DIGIT OF THE YEAR
PART NUMBER
LOT CODE
WW = WEEK
EXAMPLE: THIS IS AN IRF7101 (MOSFET)
P = DES IGNATES LEAD-FREE
PRODUCT (OPTIONAL)
A = AS SEMBLY S ITE CODE
 10 page
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IRF8910PbF
10
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Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Starting TJ = 25°C, L = 0.57mH, RG = 25Ω, IAS = 8.2A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board.
… Rθ is measured at TJ of approximately 90°C.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/04
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel
Dimensions are shown in milimeters (inches)




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