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CDC960 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 1 Page - Texas Instruments

๋ถ€ํ’ˆ๋ช… CDC960
์ƒ์„ธ๋‚ด์šฉ  200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE
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CDC960 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 1 Page - Texas Instruments

 
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CDC960
200MHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 โ€“ APRIL 2002
1
POST OFFICE BOX 655303
โ€ข DALLAS, TEXAS 75265
D Generates Clocks for AMD-K8 Clawhammer
Desktop Systems
D Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
D Includes Spread Spectrum Clocking (SSC),
0.5% Downspread for Reduced EMI
D Power Management Control Terminals
D SMBus Serial Interface Provides Output
Enable and Control
D Low-Output Skew and Low Jitter for Clock
Distribution
D Operates From Single 3.3-V Supply
D Generates the Following Clocks:
โ€“ 2 CPU (3.3 V, 180
ยฐ shifted pairs,
200/166/133/100 MHz)
โ€“ 6 PCI (3.3 V, 33 MHz)
โ€“ 1 PCI_F (3.3 V, 33 MHz)
โ€“ 3 REF (3.3 V, 14.318 MHz)
โ€“ 1 USB (3.3 V, 48 MHz)
โ€“ 1 FDC (3.3 V, 24 MHz or 48 MHz)
โ€“ 3 PCI/LDTโ€  (3.3 V, 33 MHz or 66 MHz)
D Packaged in 48-Pin SSOP Package
description
The CDC960 is a clock synthesizer/driver and
buffer that generates CPU, PCI, PCI/LDT, USB,
FDC, and REF system clock signals to support
PCs with an AMD-K8 Clawhammer-class system.
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. It is recommended to use the bypass mode of the internal oscillator in this
case. Two phase-locked loops (PLLs) are used to generate the host frequencies and 48-MHz clock frequencies.
On-chip loop filters and internal feedback eliminate the need for external components.
The device provides a standard mode (100 kbps) SMBus 1.1 serial interface for device control. The
implementation is as a slave with read and write capability. The device address is specified in the SMBus serial
interface device address table. Both SMBus inputs (SDATA and SCLK) provide integrated pullup resistors
(typically 150 k
โ„ฆ).
Seven 8-bit SMBus registers provide individual enable control for each of the outputs. The controllable outputs
default to enabled at power up and can be placed in a disabled mode with a low-level output when a low-level
control bit is written to the control register. The registers must be accessed in sequential order (i.e., random
access of the registers not supported).
The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz) clock outputs provide low-skew/low-jitter
clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control
inputs FS0, FS1, and FS2 at power-up preset condition.
Copyright
๏ฃฉ 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
โ€ LDT is equivalent to HT66 shown on AMD specification.
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FS0 & REF0
VDD
XIN
XOUT
GND
PCI/LDT_SEL
PCI/LDT0
PCI/LDT1
VDD
GND
PCI/LDT2
LDT_Stop
PCI0
PCI1
GND
VDD
PCI2
PCI3
VDD
GND
PCI4
PCI5
PCI_F
PCI_Stop
FS1 & REF1
GND
VDD
FS2 & REF2
SPREAD
VDDA
GNDA
CPU0
CPU0
GND
VDD
CPU1
CPU1
VDD
GND
GNDF
VDDF
USB
GND
VDD
24/48_SEL & FDC
GND
SDATA
SCLK
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