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TC554161AFTI-70 데이터시트(HTML) 5 Page - Toshiba Semiconductor

부품명 TC554161AFTI-70
상세내용  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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제조사  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TC554161AFTI-70 데이터시트(HTML) 5 Page - Toshiba Semiconductor

 
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TC554161AFTI-70,-85,-10,-70L,-85L,-10L
2001-08-17
5/10
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta
==== ----40° to 85°C, VDD ==== 5 V ±±±± 10%)
READ CYCLE
TC554161AFTI
-70,-70L
-85,-85L
-10,-10L
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tRC
Read Cycle Time
70
¾
85
¾
100
¾
tACC
Address Access Time
¾
70
¾
85
¾
100
tCO
Chip Enable Access Time
¾
70
¾
85
¾
100
tOE
Output Enable Access Time
¾
35
¾
45
¾
50
tBA
Data Byte Control Access Time
¾
35
¾
45
¾
50
tOH
Output Data Hold Time
10
¾
10
¾
10
¾
tCOE
Chip Enable Low to Output Active
5
¾
5
¾
5
¾
tOEE
Output Enable Low to Output Active
0
¾
0
¾
0
¾
tBE
Data Byte Control Low to Output Active
0
¾
0
¾
0
¾
tOD
Chip Enable High to Output High-Z
¾
30
¾
35
¾
40
tODO
Output Enable High to Output High-Z
¾
30
¾
35
¾
40
tBD
Data Byte Control High to Output High-Z
¾
30
¾
35
¾
40
ns
WRITE CYCLE
TC554161AFTI
-70,-70L
-85,-85L
-10,-10L
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tWC
Write Cycle Time
70
¾
85
¾
100
¾
tWP
Write Pulse Width
50
¾
55
¾
60
¾
tCW
Chip Enable to End of Write
60
¾
70
¾
80
¾
tBW
Data Byte Control to End of Write
50
¾
55
¾
60
¾
tAS
Address Setup Time
0
¾
0
¾
0
¾
tWR
Write Recovery Time
0
¾
0
¾
0
¾
tDS
Data Setup Time
30
¾
35
¾
40
¾
tDH
Data Hold Time
0
¾
0
¾
0
¾
tOEW
R/W High to Output Active
0
¾
0
¾
0
¾
tODW
R/W Low to Output High-Z
¾
30
¾
35
¾
40
ns
AC TEST CONDITIONS
PARAMETER
TEST CONDITION
Output load
100 pF
+ 1 TTL Gate
Input pulse level
0.4 V, 2.6 V
Timing measurements
1.5 V
Reference level
1.5 V
tR, tF
5 ns


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