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TC58FVT321FT-10 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 10 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TC58FVT321FT-10
์ƒ์„ธ๋‚ด์šฉ  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32-MBIT (4M X 8 BITS / 2M X 16 BITS) CMOS FLASH MEMORY
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TC58FVT321FT-10 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 10 Page - Toshiba Semiconductor

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TC58FVT321/B321FT/XB-70,-10
2002-08-06
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Program Suspend/Resume Mode
Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a
Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but
ignores the command in other modes. When the command is input, the address of the bank on which Write is
being performed must be specified. After input of the command, the device will enter Program Suspend Read
Mode after tSUSP.
During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is
suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are
the same as usual.
After completion of Program Suspend input a Program Resume command to return to Write Mode. When
inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or CFI
Data Read functions is being used, abort the function before inputting the Resume command. On receiving the
Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the
bank to which data is being written.
Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running
Program Suspend in Acceleration Mode, VACC must not be released.
Auto Chip Erase Mode
The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the
rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and
verified as erased by the chip. The device status is indicated by the Hardware Sequence flag.
Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase
operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional
Erase operation must be performed.
Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not
be executed and the device will enter Read mode 100 ยตs after the rising edge of the WE signal in the sixth bus
cycle.
If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read
Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware
reset is required to return the device to Read Mode after a failure.
In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device
altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor
must take measures to prevent subsequent use of the failed block.


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