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SLG46108 데이터시트(PDF) 50 Page - Dialog Semiconductor

부품명 SLG46108
상세설명  GreenPAK Ultra-small Programmable Mixed-signal Matrix
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Page 49 of 69
SLG46108
11.1 CNT/DLY0 Register Settings
11.2 CNT/DLY1 Register Settings
Table 39. CNT/DLY0 Register Settings
Signal Function
Register Bit
Address
Register Definition
Counter/Delay0
Mode Select
reg <301>
0: Delay Mode
1: Counter Mode
Counter/Delay0
Clock Source Select
(external clock is
only for counter
mode)
reg <305:303>
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: Reserved
111: Counter3 Overflow
Counter0 Control
Data/Delay0 Time
Control
reg <313:306>
1-255: (delay time = (counter control data +2) /freq)
Delay0 Mode Select
or asynchronous
counter reset
reg <315:314>
00: Delay on both falling and rising edges (for delay & counter reset)
01: Delay on falling edge only (for delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode
Table 40. CNT/DLY1 Register Settings
Signal Function
Register Bit
Address
Register Definition
Counter/Delay1
Mode Select
reg <318>
0: Delay Mode
1: Counter Mode
Counter/Delay1
Clock Source Select
(external clock is
only for counter
mode)
reg <322:320>
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: Reserved
111: Counter0 Output
Counter1 Control
Data/Delay1 Time
Control
reg <330:323>
1-255: (delay time = (counter control data +2) /freq)
Delay1 Mode Select
or asynchronous
counter reset
reg <332:331>
00: Delay on both falling and rising edges (for delay & counter reset)
01: Delay on falling edge only (for delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode


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