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SLG46140 데이터시트(PDF) 39 Page - Dialog Semiconductor |
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SLG46140 데이터시트(HTML) 39 Page - Dialog Semiconductor |
39 / 170 page 000-0046140-109 Page 38 of 169 SLG46140 7.0 I/O Pins The SLG46140 has a total of 12 general purpose I/O pins (GPIO) which can be configured as either Input or Output, some with special functions (such as outputting the Vref), or serving as a signal for programming of the on-chip NVM. Normal Mode pin definitions are as follows: • Pin 1: VDD Power Supply • Pin 2: General Purpose Input (GPI) • Pin 3: GPIO with Output Enable (OE) • Pin 4: GPIO with OE, ACMP0(-) Input, PGA Output • Pin 5: GPIO with OE, ACMP1(-) Input • Pin 6: GPIO without OE, PGA(+) • Pin 7: GPIO with OE, PGA(-) • Pin 8: GND • Pin 9: GPIO with OE, 4x Drive Output, ACMP1(+) Input • Pin 10: GPIO, 4x Drive Output, ACMP0(+) Input • Pin 11: GPIO, ADC Channel Select • Pin 12: GPIO with OE • Pin 13: GPIO with OE • Pin 14: GPIO with OE Programming Mode pin definitions are as follows: • Pin 1: VDD Power Supply • Pin 2: VPP Programming Voltage • Pin 3: RTSB • Pin 10: Programming Mode Control • Pin 11: Programming ID • Pin 12: Programming SDIO • Pin 13: Programming SRDWB • Pin 14: Programming SCL 7.1 Input Modes Digital Input Each GPI, GPIO pin can be configured as a: • Digital input with/without buffered Schmitt Trigger • Low Voltage Digital Input (LVDI) Pin 2 can function as a RESET pin Analog Input • Pin 3 can function as an analog input for the ADC Vref • Pins 4, 5, 9, 10 can function as analog inputs for the ACMPs • Pins 6 and 7 can function as analog input for PGA(+) and PGA(-), respectively 7.2 Output Modes Pins 3, 4, 5, 9, 12, 13, and 14 can be configured as a digital output with 1x/2x push pull, 1x/2x Open Drain NMOS, or 1x/2x 3-state output with output enable. |
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