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SLG46140 데이터시트(PDF) 87 Page - Dialog Semiconductor |
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SLG46140 데이터시트(HTML) 87 Page - Dialog Semiconductor |
87 / 170 page 000-0046140-109 Page 86 of 169 SLG46140 12.4.1 3-Bit LUT or 8-Bit Counter / Delay Macrocells Used as 3-Bit LUT Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function: 3-Bit LUT7 is defined by reg<668:661> 12.4.2 3-Bit LUT or as 8-Bit Counter / Delay Register Settings Table 58. CNT/DLY2 Register Settings Signal Function Register Bit Address Register Definition Counter/delay/FSM Control Data reg <668:661> 1 – 256 (delay time = (counter control data +2.5) /freq) Counter/delay/FSMQ mode reg <669> 0: Reset to 0s 1: Set to Data Counter/delay/FSM Clock Source Select reg <673:670> 0000: CK_RCOSC 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64 0101: CNT_END2 0110: matrix_out67 0111: matrix_out67 divide by 8 1000: CK_RINGOSC 1001: matrix_out80(SPI_SCLK) 1010: CK_LFOSC 1011: CKFSM_DIV256 1100: CKPWM 1101: Reserved 1110: Reserved 1111: Reserved Delay Mode Select or asynchronous counter reset reg <675:674> 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset Delay) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode Counter/delay/FSM or LUT3_7 Macrocell Function Select reg <677:676> 00: Delay mode 01: Counter/FSM mode 10: Edge Detect mode 11: LUT3_7 Table 57. 3-bit LUT6 Truth Table IN2 IN1 IN0 OUT 0 0 0 reg <661> 0 0 1 reg <662> 0 1 0 reg <663> 0 1 1 reg <664> 1 0 0 reg <665> 1 0 1 reg <666> 1 1 0 reg <667> 1 1 1 reg <668> |
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