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OP215 데이터시트(PDF) 3 Page - Analog Devices

부품명 OP215
상세설명  Dual Precision JFET-Input Operational Amplifier
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OP215 데이터시트(HTML) 3 Page - Analog Devices

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REV. A
–2–
OP215–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
OP215E
OP215G
Parameter
Symbol
Conditions
Min
Type
Max
Min
Type
Max
Unit
Input Offset Voltage
VOS
RS = 50
W
0.2
1.0
2.0
4.0
mV
‘G’ Grade
2.5
6.0
mV
Input Offset Current
1
IOS
Tj = 25
∞C3
50
3
100
pA
Device Operating
5
100
5
200
pA
Input Bias Current
1
IB
Tj = 25
∞C
±15
±100
±15
±300
pA
Device Operating
±18
±300
±18
±600
pA
Input Resistance
RIN
10
1,2
10
1,2
W
Large-Signal Voltage
AVO
RL
2 k
W,
150
500
50
200
V/mV
Gain
VO =
±10 V
Output Voltage Swing
VO
RL = 10 k
W±12
±13
±12
±13
V
RL = 2 k
W±11
±12.7
±11
±12.7
V
Supply Current
ISY
6.0
8.5
7.0
10.0
mA
‘G’ Grade
7.0
12.0
mA
Slew Rate
SR
AVCL = 1
10
18
5
15
V/ s
Gain Bandwidth
GBW
3.5
5.7
3.0
5.4
MHz
Product3
Closed-Loop Bandwidth CLBW
AVCL = 1
13
12
MHz
Setting Time
tS
To 0.01%
2.3
2.4
s
To 0.05%
2
1.1
1.2
s
To 0.10%
0.9
1.0
s
Input Voltage Range
IVR
10.2
14.8
10.1
14.8
V
–10.2
–11.5
–10.1
–11.5
V
Common-Mode
CMRR
VCM =
±IVR
82
100
80
96
dB
Rejection Ratio
E, G Grades
Power Supply Rejection
PSRR
VS =
±10 V to ±16 V
10
51
V/V
Ratio
VS =
±10 V to ±15 V
16
100
V/V
Input Noise Voltage
nfO = 100 Hz
20
20
nV/
÷Hz
Density
fO = 1,000 Hz
15
15
nV/
÷Hz
Input Noise Current
In
fO = 100 Hz
0.01
0.01
pA/
÷Hz
Density
fO = 1,000 Hz
0.01
0.01
pA/
÷Hz
Input Capacitance
CIN
33
pF
NOTES
1Input bias current is specified for two different conditions. The T
j = 25
∞C specification is with the junction at ambient temperature; the device operating specification is
with the device operating in a warmed up condition at 25
∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves
of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard
JFET input op amps. IS and IOS are measured at VCM = 0.
2Setting time is defined here for a unity gain inverter connection using 2 k
W resistors. It is the time required for the error voltage (the voltage at the inverting input pin
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See setting time test circuit.
3Sample tested.
Specifications are subject to change without notice.
(at VS =
±15 V, TA = 25 C, unless otherwise noted.)


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