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NE33200M 데이터시트(PDF) 1 Page - NEC |
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NE33200M 데이터시트(HTML) 1 Page - NEC |
1 / 7 page SUPER LOW NOISE HJ FET NE33200 PART NUMBER NE33200 PACKAGE OUTLINE 00 (Chip) SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX NFOPT1 Noise Figure, VDS = 2 V, ID = 10 mA, f = 4 GHz dB 0.35 f = 12 GHz dB 0.75 1.0 GA1 Associated Gain, VDS = 2 V, ID = 10 mA, f = 4 GHz dB 15.0 f = 12 GHz dB 9.5 10.5 P1dB Output Power at 1 dB Gain Compression Point, f = 12 GHz VDS = 2 V, IDS = 10 mA dBm 11.2 VDS = 2 V, IDS = 20 mA dBm 12.0 G1dB Gain at P1dB, f = 12 GHz VDS = 2 V, IDS = 10 mA dB 11.8 VDS = 2 V, IDS = 20 mA dB 12.8 IDSS Saturated Drain Current, VDS = 2 V, VGS = 0 V mA 15 40 80 VP Pinch-off Voltage, VDS = 2 V, ID = 100 µA V -2.0 -0.8 -0.2 gm Transconductance, VDS = 2 V, ID = 10 mA mS 45 70 IGSO Gate to Source Leakage Current, VGS = -5 V µA0.5 10 RTH(CH-C)2 Thermal Resistance (Channel to Case) °C/W 240 Notes: 1.RF performance is determined by packaging and testing 10 samples per wafer.Wafer rejection criteria for standard devices is 2 rejects for 10 samples. 2. Chip mounted on infinite heat sink. DESCRIPTION The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create a two-dimensional electron gas layer with very high electron mobility. Its excellent low noise figure and high associated gain make it suitable for commercial and industrial applications. NEC's stringent quality assurance and test procedures as- sure the highest reliability and performance. FEATURES • VERY LOW NOISE FIGURE: 0.75 dB typical at 12 GHz • HIGH ASSOCIATED GAIN: 10.5 dB Typical at 12 GHz • GATE LENGTH: 0.3 µm • GATE WIDTH: 280 µm ELECTRICAL CHARACTERISTICS (TA = 25°C) Frequency, f (GHz) NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA California Eastern Laboratories 4 3.5 3 2.5 2 1.5 1 0.5 0 Ga NF 1 10 30 24 21 18 15 12 9 6 3 0 |
유사한 부품 번호 - NE33200M |
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유사한 설명 - NE33200M |
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