2001 Apr 06

2

Philips Semiconductors

Preliminary specification

2-input EXCLUSIVE-OR gate

74LVC1G86

FEATURES

• Wide supply voltage range from 1.65 to 5.5 V

• High noise immunity

• Complies with JEDEC standard:

– JESD8-7 (1.65 to 1.95 V)

– JESD8-5 (2.3 to 2.7 V)

– JESD8B/JESD36 (2.7 to 3.6 V).

• CMOS low power consumption

• Latch-up performance ≤250 mA

• Direct interface with TTL levels

• SOT353 package.

DESCRIPTION

The 74LVC1G86 is a high-performance, low-power,

low-voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. These

features allow the use of these devices in a mixed

3.3 and 5 V environment.

This device is fully specified for partial power-down

preventing the damaging backflow current through the

device when it is powered down.

The 74LVC1G86 provides the 2-input EXCLUSIVE-OR

function.

QUICK REFERENCE DATA

Notes

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

propagation delay A and B to Y

3.7

ns

2.5

ns

2.3

ns

1.9

ns

input capacitance

5

pF

power dissipation capacitance per

buffer

notes 1 and 2

25

pF