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LM3713XW4BP308 데이터시트(PDF) 2 Page - National Semiconductor (TI) |
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LM3713XW4BP308 데이터시트(HTML) 2 Page - National Semiconductor (TI) |
2 / 13 page Connection Diagram Top View (looking from the coating side) micro SMD 9 Bump Package BPA09 20011901 Pin Description Bump No. Name Function A1 MR Manual-Reset input. When MR is less than V MRT (Manual Reset Threshold) RESET/RESET is engaged. B1 V CC Power Supply input. C1 RESET Reset Logic Output. Pulses low for t RP (Reset Timeout Period) when triggered, and stays low whenever V CC is below the reset threshold or when MR is below VMRT. It remains low for t RP after either VCC rises above the reset threshold, or after MR input rises above V MRT (LM3712 only). RESET Reset Logic Output. RESET is the inverse of RESET (LM3713 only). C2 PFO Power-Fail Logic Output. When PFI is below V PFT PFO goes low; otherwise, PFO remains high. C3 WDO Watchdog Output. If no digital activity is detected on WDI (Watchdog Input) for a period exceeding t WD, this output pulls low. B3 GND Ground reference for all signals. A3 WDI Watchdog Input Transition Monitor: If no transition activity occurs for a period exceeding t WD (Watchdog Timeout Period), reset is engaged. A2 PFI Power-Fail Comparator Input. When PFI is less than V PFT (Power-Fail Reset Threshold), the PFO goes low; otherwise, PFO remains high. B2 NC No Connect. Test input used at factory only. Leave floating. www.national.com 2 |
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