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AD9058AKD 데이터시트(PDF) 7 Page - Analog Devices |
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AD9058AKD 데이터시트(HTML) 7 Page - Analog Devices |
7 / 12 page REV. AD9058 –6– THEORY OF OPERATION The AD9058 contains two separate 8-bit analog-to-digital con- verters (ADCs) on a single silicon die. The two devices can be operated independently with separate analog inputs, voltage references, and clocks. In a traditional flash converter, 256 input comparators are required to make the parallel conversion for 8-bit resolution. This is in marked contrast to the scheme used in the AD9058, as shown in Figure 1. Unlike traditional “flash,” or parallel, converters, each of the two ADCs in the AD9058 utilizes a patented interpolating archi- tecture to reduce circuit complexity, die size, and input capacitance. These advantages accrue because, compared to a conventional flash design, only half the normal number of input comparator cells is required to accomplish the conversion. In this unit, each of the two independent ADCs uses only 128 (2 7) comparators to make the conversion. The conversion for the seven most significant bits (MSBs) is performed by the 128 comparators. The value of the least significant bit (LSB) is determined by interpolation between adjacent comparators in the decoding register. A proprietary decoding scheme processes the comparator outputs and provides an 8-bit code to the output register of each ADC; the scheme also minimizes error codes. 8 256 ANALOG IN –VREF +VREF 8 128 127 2 1 Figure 1. Comparator Block Diagram Analog input range is established by the voltages applied at the voltage reference inputs (+VREF and –VREF). The AD9058 can operate from 0 V to 2 V using the internal voltage reference, or anywhere between –1 V and +2 V using external references. Input range is limited to 2 V p-p when using external references. The internal resistor ladder divides the applied voltage reference into 128 steps, with each step representing two 8-bit quanti- zation levels. COMP ENCODE A ENCODE +VINT AIN A +VS D0A(LSB) –VS D0B(LSB) D7A(MSB) AIN B D7B(MSB) AD9058 (J-LEAD) –VREF A –VREF B ENCODE B +VREF A +VREF B CLOCK ANALOG IN A 0.5V ANALOG IN B 0.5V 0.1 F 0.1 F +5V –5V 0.1 F –2V +2V AD9617 400 400 20k 200 200 800 800 20k 5 5 0.1 F 10pF 1k 50 (SEE TEXT) CLOCK 8 8 1N4001 4, 19, 21, 25, 27, 42 40 1 43 3 2 6 38 8 7, 20, 26, 39 28 29 30 31 32 33 34 35 18 17 16 15 14 13 12 11 5, 9, 22, 24, 37, 41 10 36 AD9617 AD707 74HCT04 Figure 2. AD9058 Using Internal 2 V Voltage Reference E |
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