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Issue A

LANSDALE Semiconductor, Inc.

ML145488

System Master (DMA) Mode

During DMA operation, the DDLC becomes a system master

and controls the system bus. When one of the internal FIFOs

requests a DMA transfer, the DDLC negotiates with the system

host for ownership of the bus. After successful negotiation, one

DMA request is serviced, and then the bus is relinquished. The

DDLC has the capability of reading or writing data from or to

memory. If the memory system is slow, the DDLC inserts wait

states (user selectable) until the memory is ready to complete the

access. The DDLC has the capability of recovering from system

faults such as addressor bus errors.

Interrupt Operation

The DDLC has 27 vectored interrupt sources to inform the host

of its status. One group of interrupts is normal operation inter-

rupts. These inform the host that a particular task was completed

and that new tasks are desired. Another group is bit handler faults,

which inform the host that a DDLC channel detected a fault from

which it cannot recover without assistance from the host. A third

group is the timer and SCP interrupts. The last group of interrupts

is the system faults. These include DMA bus and address errors.

The interrupts are presented to the host as a vector number in an

interrupt acknowledge cycle. The interrupts are encoded into the

low four bits so the DDLC vector space consumes 16 out of 256

locations. Software can program the base vector number, so the

DDLC vectors can be located anywhere within the vector table.

For applications not using vectored interrupts, the equivalent vec-

tor number is accessible in the Master Status register.

SERIAL INTERFACE

The serial interface block has a variety of configurations that

make it compatible with most common interfaces. Each serial inter-

face is independent, so two different configurations may be active

simultaneously. The serial interface has an IDL mode, a time slot

mode, and a general purpose modem mode. The serial interface

supports long frame and short frame timing. It also supports sub-

rate multiplexing. The serial mode is selected by programming the

appropriate bits in the Serial Interface Control register.

A full set of serial interface control and handshake pins are pro-

vided. The name and functionality change to reflect The serial

mode of operation. Separate receive and transmit clock inputs are

provided for all modes except IDL and time-slot modes.

The serial interface also supports transfer of transparent data.

Depending on which type of serial interface is used, an external

synchronization signal must be provided to maintain byte align-

ment. In IDL mode, the byte synchronization is programmed by

the microprocessor.

SERIAL CONTROL PORT

A Serial Control Port, similar to the Serial Peripheral Interface

(SPI) on Motorola single–chip microprocessors, is provided to

communicate with external devices via a serial link. The SCP

functions are multiplexed onto other serial pins so when the SCP

is enabled, certain modem control features are lost. Please consult

Lansdale Semiconductor for more detailed technical information.

TIMERS

Two timers are provided for general purpose low–resolution

protocol uses. The clock to the timer is derived from the Master

MPU Clock (MCLK). The baud rate generator in the SCP block is

used to drive the timer divide chain. This clock is then divided by

1024 and applied to an eight–bit down–counter. The counter is

readable and writable by the host and may be set to any value.

The counter counts down toward zero from the current value. A

non–maskable interrupt is generated when the counter underflows

from FF to FE. The timers continue counting down after reaching

FE. The status bit from the previous interrupt must be cleared

before a new interrupt is generated. The timer function and inter-

rupt are enabled by setting the Timer Enable bit in the Timer reg-

ister to one. The timer interrupt status bits must be read while set

before they can be cleared. The timers are intended for low accu-

racy uses such as protocol timers. Figure 8 describes the clock

selection choices for the timers.

Watchdog Timer

Timer 0 may be configured as a watchdog timer for the entire

host system. When the Watchdog Enable bit is set, an extra

divide–by–16 is added to the clock input of the counter. When the

counter underflows from FF to FE, the Reset pin becomes an out-

put for 16 MCLK cycles and a logic low is output. This provides a

system reset to the host. The host can write any value (except FE

hex) to the Timer register to setup any timeout. Timeouts of up to

5.6 seconds are available with a 12 MHz MCLK.

POWER CONSUMPTION

The DDLC is designed utilizing high–performance CMOS

technology. As as result, average power consumption is very low.

However, because there are wide address and databuses, peak cur-

rents may exceed 150 mA for short periods of time (less than 20

ns) while the drivers are charging or discharging the buses.

REGISTER SET

The DDLC has many user accessible registers. These registers

control the blocks or indicate status. Other registers, used by the

DMA section, are used as buffer descriptors and counters. For a

more detailed description, please refer to the DDLC data book.

The address for each register is the hexadecimal offset from the

base address of the chip select. The registers may be accessed as

8–bit registers or 16–bit registers. Table 1 is a map of the registers

and their principal function.